公开(公告)号：US07791357B2

公开(公告)日：2010-09-07

申请号：US11722629

申请日：2005-12-19

申请人： Praveen Pavithran ,  Marcel Pelgrom ,  Jean Wieling ,  Hendricus Joseph Veendrick

发明人： Praveen Pavithran ,  Marcel Pelgrom ,  Jean Wieling ,  Hendricus Joseph Veendrick

IPC分类号： G01R27/26

CPC分类号： G01R31/2853 ,  G01R27/2605

摘要： The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.

摘要翻译： 本发明涉及一种用于硅互连电容（Cx）提取的片上电路，其被自适应于集成晶体管中的工艺变化。 电路（10）包括信号产生装置（20），用于产生连接到第一和第二信号延迟装置（31,32）的周期性脉冲信号，用于各自延迟所述脉冲信号，其中所述第二信号延迟装置（32）被配置 具有由所述互连电容（Cx）影响的延迟; 用于连接所述各个第一和第二延迟装置（31,32）的相应第一和所述第二延迟信号的逻辑异或门（35），所述逻辑异或门（35）连接到信号积分装置（40）; 并且所述信号积分装置（40）连接到模数转换装置（50）。 虽然传统的无补偿系统中的误差，如延迟线，误差可以高达30％，但在根据本发明的电路中，由于前端处理变化引起的误差约为2％。 此外，以数字格式提供输出，因此可以用简单的外部硬件快速测量。 此外，脉冲信号频率可以用作监视器来测量前端的过程变化。 此外，由于电路（10）非常准确且非常容易测量，因此作为未来制造的每个芯片的过程监视器是最佳选择。

公开(公告)号：US20080143348A1

公开(公告)日：2008-06-19

申请号：US11722629

申请日：2005-12-19

申请人： Praveen Pavithran ,  Marcel Pelgrom ,  Jean Wieling ,  Hendricus Joseph Veendrick

发明人： Praveen Pavithran ,  Marcel Pelgrom ,  Jean Wieling ,  Hendricus Joseph Veendrick

IPC分类号： G01R27/26

CPC分类号： G01R31/2853 ,  G01R27/2605

摘要： The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.

摘要翻译： 本发明涉及一种用于硅互连电容（Cx）提取的片上电路，其被自适应于集成晶体管中的工艺变化。 电路（10）包括信号产生装置（20），用于产生连接到第一和第二信号延迟装置（31,32）的周期性脉冲信号，用于各自延迟所述脉冲信号，其中所述第二信号延迟装置（32）被配置 具有由所述互连电容（Cx）影响的延迟; 用于连接所述各个第一和第二延迟装置（31,32）的相应第一和所述第二延迟信号的逻辑异或门（35），所述逻辑异或门（35）连接到信号积分装置（40）; 并且所述信号积分装置（40）连接到模数转换装置（50）。 虽然传统的无补偿系统中的误差，如延迟线，误差可以高达30％，但在根据本发明的电路中，由于前端处理变化引起的误差约为2％。 此外，以数字格式提供输出，因此可以用简单的外部硬件快速测量。 此外，脉冲信号频率可以用作监视器来测量前端的过程变化。 此外，由于电路（10）非常准确且非常容易测量，因此作为未来制造的每个芯片的过程监视器是最佳选择。