公开(公告)号：US06539523B1

公开(公告)日：2003-03-25

申请号：US09566692

申请日：2000-05-08

Applicant: Prakash Narain ,  Jay Andrew Littlefield ,  Christopher Richard Morrison ,  Rajeev Kumar Ranjan

Inventor： Prakash Narain ,  Jay Andrew Littlefield ,  Christopher Richard Morrison ,  Rajeev Kumar Ranjan

IPC: G06F1750

CPC classification number: G06F17/5022

Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a comprehensive set of design verification checks may be formulated by applying predetermined properties to an annotated hardware design representation. Information regarding the intended flow of logical signals in the hardware design is received by way of annotations in a control file or annotations embedded in the hardware design representation itself. The annotations include (1) an indication of one or more variables in the representation of the hardware design through which the logical signals pass, and (2) an indication of one or more conditions under which each of the one or more variables are to be associated with each of a set of states. Checks are then automatically formulated based upon a predetermined set of properties that must hold true in order for the hardware design to operate in accordance with the intended flow. Each of the checks is capable of evaluation with reference to the states associated with the one or more variables during propagation of the logical signals.

Abstract translation: 提供了一种便于在设计中的关键点之间分析逻辑信号的预期流程的方法和装置。 根据本发明的一个方面，可以通过对注释的硬件设计表示应用预定属性来形成一整套设计验证检查。 关于硬件设计中的逻辑信号的预期流程的信息通过嵌入在硬件设计表示本身中的控制文件或注释中的注释来接收。 注释包括（1）逻辑信号通过的硬件设计的表示中的一个或多个变量的指示，以及（2）一个或多个变量中的每个变量将被表示为的一个或多个条件的指示 与一组状态中的每一个相关联。 然后，根据必须符合的预定的一组属性自动制定检查，以便硬件设计根据预期的流程进行操作。 参考在逻辑信号传播期间与一个或多个变量相关联的状态，每个检查能够进行评估。

公开(公告)号：US08731894B1

公开(公告)日：2014-05-20

申请号：US13618632

申请日：2012-09-14

Applicant: Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Lawrence Loh ,  Beth C. Isaksen ,  Yann Alain Antonioli ,  Craig Franklin Deaton

Inventor： Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Lawrence Loh ,  Beth C. Isaksen ,  Yann Alain Antonioli ,  Craig Franklin Deaton

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract translation: 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它有助于当前的设计和验证工作，以及设计重用。

公开(公告)号：US08630824B1

公开(公告)日：2014-01-14

申请号：US12797468

申请日：2010-06-09

Applicant: Chung-Wah Norris Ip ,  Kathryn Drews Kranen ,  Rajeev Kumar Ranjan ,  Beth C. Isaksen ,  Karl Stefan Esbjörner ,  Craig Franklin Deaton

Inventor： Chung-Wah Norris Ip ,  Kathryn Drews Kranen ,  Rajeev Kumar Ranjan ,  Beth C. Isaksen ,  Karl Stefan Esbjörner ,  Craig Franklin Deaton

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract translation: 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它有助于当前的设计和验证工作，以及设计重用。

公开(公告)号：US09477802B1

公开(公告)日：2016-10-25

申请号：US12797476

申请日：2010-06-09

Applicant: Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Kathryn Drews Kranen ,  Beth C. Isaksen ,  Georgia Penido Safe

Inventor： Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Kathryn Drews Kranen ,  Beth C. Isaksen ,  Georgia Penido Safe

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract translation: 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它设计了当前的设计和验证工作，以及设计重用。

公开(公告)号：US08458621B1

公开(公告)日：2013-06-04

申请号：US12797471

申请日：2010-06-09

Applicant: Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Georgia Penido Safe ,  Claudionor José Nunes Coelho ,  Yann Alain Antonioli

Inventor： Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Georgia Penido Safe ,  Claudionor José Nunes Coelho ,  Yann Alain Antonioli

IPC: G06F17/50

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

公开(公告)号：US08205187B1

公开(公告)日：2012-06-19

申请号：US12797473

申请日：2010-06-09

Applicant: Claudionor José Nunes Coelho ,  Chung-Wah Norris Ip ,  Harry David Foster ,  Rajeev Kumar Ranjan ,  Kathryn Drews Kranen ,  Georgia Penido Safe

Inventor： Claudionor José Nunes Coelho ,  Chung-Wah Norris Ip ,  Harry David Foster ,  Rajeev Kumar Ranjan ,  Kathryn Drews Kranen ,  Georgia Penido Safe

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract translation: 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它有助于当前的设计和验证工作，以及设计重用。

公开(公告)号：US08831925B1

公开(公告)日：2014-09-09

申请号：US12797467

申请日：2010-06-09

Applicant: Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Lawrence Loh ,  Beth C. Isaksen ,  Yann Alain Antonioli ,  Craig Franklin Deaton

Inventor： Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Lawrence Loh ,  Beth C. Isaksen ,  Yann Alain Antonioli ,  Craig Franklin Deaton

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

公开(公告)号：US08527911B1

公开(公告)日：2013-09-03

申请号：US12797471

申请日：2010-06-09

Applicant: Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Georgia Penido Safe ,  Claudionor José Nunes Coelho ,  Yann Alain Antonioli

Inventor： Kathryn Drews Kranen ,  Chung-Wah Norris Ip ,  Rajeev Kumar Ranjan ,  Georgia Penido Safe ,  Claudionor José Nunes Coelho ,  Yann Alain Antonioli

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract translation: 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它有助于当前的设计和验证工作，以及设计重用。

公开(公告)号：US07092858B1

公开(公告)日：2006-08-15

申请号：US10046220

申请日：2002-01-16

Applicant: James Herbert Kukula ,  Thomas Robert Shiple ,  Rajeev Kumar Ranjan

Inventor： James Herbert Kukula ,  Thomas Robert Shiple ,  Rajeev Kumar Ranjan

IPC: G06F17/10

CPC classification number: G06F17/504 ,  G06F17/5022

Abstract: In a finite state machine (FSMverify) a set of goal states, to be searched for their reachability from a start state, is defined.An overapproximated path is found from a start state to a goal state by a forward approximation technique. The overapproximated path representation relies upon a partitioning of the state and input bits of FSMverify. A state matrix of the overapproximated path is organized by time-steps of FSMverify along a first dimension and by partitions of FSMverify state bits along a second dimension.An underapproximated path, along the path of the stepping stone matrix, is determined. Underapproximation is typically accomplished by simulation.A sequence of states to be output is updated with the underapproximated path.If a start to goal state sequence has been found, the procedure ends. Otherwise, the above steps of over and under approximation are repeated, using the results of the last underapproximation as a start state.

Abstract translation: 在有限状态机（FSM <验证）中，定义了从起始状态搜索其可达性的一组目标状态。 通过前向近似技术从起始状态到目标状态发现过近似路径。 过近似路径表示依赖于FSM _{验证的状态和输入位的划分。 过近似路径的状态矩阵通过沿第一维度的FSM验证的时间步长和沿着第二维度的FSM确认状态位的分段来组织。 确定沿着垫脚石矩阵的路径的未近似路径。 通常通过模拟来实现欠近似。 要输出的状态序列用不正确的路径更新。 如果已经找到目标状态序列的开始，则过程结束。 否则，使用最后一次不足近似的结果作为开始状态重复上述和过度近似的步骤。}