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1.发明申请BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE 有权内置自测试方法，电路和装置，用于具有动态可配置的测试结构的RF模块的同时测试公开(公告)号：US20120191400A1
公开(公告)日：2012-07-26
申请号：US13042849
申请日：2011-03-08
Applicant: Adesh Sharadrao Sontakke , Rajesh Kumar Mittal , Rubin A. Parekhji , Upendra Narayan Tripathi
Inventor： Adesh Sharadrao Sontakke , Rajesh Kumar Mittal , Rubin A. Parekhji , Upendra Narayan Tripathi
IPC: G06F19/00
CPC classification number: G01R31/31917 , G01R31/31716 , G01R31/31724
Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.
Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 与所述存储电路（110）和所述功能电路模块（IP.i）耦合的芯片测试控制器（140,150），所述测试控制器（140,150）可操作以动态地调度和触发这些组中的测试，由此 促进在所述功能电路模块（IP.i）中并行执行测试。 公开了其他电路，无线芯片，系统以及操作过程和制造过程。
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2.发明授权Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure 有权内置自检方法，电路和设备，用于通过动态配置的测试结构对射频模块进行并发测试公开(公告)号：US08694276B2
公开(公告)日：2014-04-08
申请号：US13042849
申请日：2011-03-08
Applicant: Adesh Sharadrao Sontakke , Rajesh Kumar Mittal , Rubin A. Parekhji , Upendra Narayan Tripathi
Inventor： Adesh Sharadrao Sontakke , Rajesh Kumar Mittal , Rubin A. Parekhji , Upendra Narayan Tripathi
IPC: G06F19/00
CPC classification number: G01R31/31917 , G01R31/31716 , G01R31/31724
Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.
Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 与所述存储电路（110）和所述功能电路模块（IP.i）耦合的芯片测试控制器（140,150），所述测试控制器（140,150）可操作以动态地调度和触发这些组中的测试，由此 促进在所述功能电路模块（IP.i）中并行执行测试。 公开了其他电路，无线芯片，系统以及操作过程和制造过程。
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