公开(公告)号：US20180143301A1

公开(公告)日：2018-05-24

申请号：US15817285

申请日：2017-11-20

申请人： Vipul Dutt Badoni ,  Michael Patrick Lenihan ,  Michael John Henderson ,  Boping Xie ,  Michael V. Morelli ,  Randy Goettsch

发明人： Vipul Dutt Badoni ,  Michael Patrick Lenihan ,  Michael John Henderson ,  Boping Xie ,  Michael V. Morelli ,  Randy Goettsch

IPC分类号： G01S7/481 ,  G01S17/06

CPC分类号： G01S7/4813 ,  G01S7/4815 ,  G01S7/4817 ,  G01S7/484 ,  G01S17/06 ,  G01S17/42

摘要： An apparatus comprises a horizontal array of emitter/detector pairs; an array of lens pairs mounted above and aligned with emitter/detector pairs; and a first curved reflective surface positioned such that for each emitter/detector pair and corresponding lens pair, light from the emitter that passes through a lens of the lens pair is redirected into the far field, and light arriving from the far field is redirected through the other lens of the lens pair onto the detector. Light from each emitter is emitted upwards along a vertical axis, and light received by each detector is incident on the detector downwards along a vertical axis. If light emitted from the first array and reflected by the first surface into the far field reflects off an object in the far field and returns to the apparatus, the returning light is reflected off the first surface and detected by the first array.

公开(公告)号：US4773044A

公开(公告)日：1988-09-20

申请号：US933715

申请日：1986-11-21

申请人： Adrian Sfarti ,  Randy Goettsch

发明人： Adrian Sfarti ,  Randy Goettsch

IPC分类号： G09G5/00 ,  G06F3/153 ,  G06F12/00 ,  G06F12/06 ,  G06T1/60 ,  G09G1/02 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/18 ,  G11C11/401 ,  G06F13/00

CPC分类号： G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00

摘要： An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

摘要翻译： 一种阵列字组织的存储器系统，包括多个列和行的存储器芯片，通过所有存储器芯片布线的地址总线，多条可选择的CAS线，其中一条CAS线路经过所述多个 的存储器芯片的列和多个可选择的RAS线，其中RAS线之一被路由通过所述多行存储器芯片中的每一行。 在操作中，选择的X和Y地址与在四个连续时间段期间选择的CAS和RAS线的选通一起被施加到​​存储器芯片，用于寻址存储在存储器芯片中的任意阵列的像素。

公开(公告)号：US4914622A

公开(公告)日：1990-04-03

申请号：US40519

申请日：1987-04-17

申请人： Adrian Sfarti ,  Randy Goettsch

发明人： Adrian Sfarti ,  Randy Goettsch

IPC分类号： G06F5/01 ,  G06T1/60

CPC分类号： G06F5/01 ,  G06T1/60

摘要： A graphics processor having a bit map comprising a plurality of memory planes is provided with an 8.times.8 barrel shifter which is responsive to a plurality of control signals for selectively shifting bits within the planes and/or between planes.

摘要翻译： 具有包括多个存储器平面的位图的图形处理器设置有8×8桶形移位器，其响应于多个控制信号，用于选择性地移动平面内和/或平面之间的位。