公开(公告)号：US06865616B1

公开(公告)日：2005-03-08

申请号：US09649792

申请日：2000-08-29

Applicant: Thomas G. Adams ,  Randy R. Fuller

Inventor： Thomas G. Adams ,  Randy R. Fuller

IPC: H04B7/185 ,  G08F15/16

CPC classification number: H04B7/18584

Abstract: A method and system are provided for processing a data transport stream. The transport stream is parsed to derive multiple elementary substreams, each of which includes a received media access control address. The received media access control address is then compared in hardware against several stored media access control addresses.

Abstract translation: 提供了一种处理数据传输流的方法和系统。 解析传输流以导出多个基本子流，每个子流包括接收到的媒体访问控制地址。 然后，所接收的媒体访问控制地址在硬件中与若干存储的媒体访问控制地址进行比较。

公开(公告)号：US5802561A

公开(公告)日：1998-09-01

申请号：US671154

申请日：1996-06-28

Applicant: Thomas F. Fava ,  Joseph M. Keith ,  Randy R. Fuller

Inventor： Thomas F. Fava ,  Joseph M. Keith ,  Randy R. Fuller

IPC: G06F11/20 ,  G06F12/08 ,  G11C29/00

CPC classification number: G06F11/2087 ,  G11C29/74 ,  G06F12/0866

Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

Abstract translation: 计算系统中的高速缓冲存储器系统具有存储数据的第一高速缓存模块，存储数据的第二高速缓存模块和控制器同时向第一和第二高速缓存模块写入数据。 可以添加第二控制器以将数据同时写入第一和第二高速缓存模块。 在单个写周期中，每个控制器请求访问第一和第二缓存模块。 两个缓存模块都将缓存请求的确认发送回控制器。 响应于来自两个缓存模块的确认的每个控制器同时向两个缓存模块发送相同的数据。 两个缓存模块在相应的缓存模块中将相同的数据写入高速缓存。

公开(公告)号：US07069574B1

公开(公告)日：2006-06-27

申请号：US09650329

申请日：2000-08-29

Applicant: Thomas G Adams ,  Randy R Fuller

Inventor： Thomas G Adams ,  Randy R Fuller

IPC: H04N7/20

CPC classification number: H04N21/6143 ,  H04N7/20 ,  H04N21/4305

Abstract: A method and system are provided for synchronizing a digital video system that includes a transmitter, a receiver, and a decoder. A transport packet is received from the transmitter. At the start of receiving the transport packet, a system time clock timestamp is captured. A program clock reference timestamp is also obtained from the transport packet and is compared with the system time clock timestamp.

Abstract translation: 提供了一种用于同步包括发射机，接收机和解码器的数字视频系统的方法和系统。 从发射机接收传输分组。 在接收到传输分组的开始时，捕获系统时间时间戳。 还从传输分组获得节目时钟参考时间戳，并与系统时钟时间戳进行比较。