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公开(公告)号：US07647567B1
公开(公告)日：2010-01-12
申请号：US11047329
申请日：2005-01-31
CPC分类号： G06F17/505 , G06F17/504
摘要： A system and method for Term Rewriting System hardware design employs a scheduler that incorporates a preference order in scheduling conflicting rules. The scheduler schedules a conflicting rule to execute when its predicate is true, and it is preferred over other conflicting rules in the preference order. The preference order may be, in one embodiment, a user-specified preference order enumerated by a designer. Such an order may be chosen according to efficiency criteria, such that the conflicting rule most essential for efficient hardware will be scheduled to execute on a given state rather than less essential conflicting rules The system and method advantageously permits a schedule to be computed in a time frame polynomially related to the number of rules, and produces more predictable and more easily understood schedules than conventional methods.
摘要翻译： 用于术语重写系统硬件设计的系统和方法使用调度器，该调度器在调度冲突规则中包含偏好顺序。 调度器调度冲突规则以在其谓词为真时执行，并且优先于优先级顺序中的其他冲突规则。 在一个实施例中，偏好顺序可以是由设计者枚举的用户指定的偏好顺序。 这样的顺序可以根据效率标准来选择，使得对有效硬件最重要的冲突规则将被调度为在给定状态下执行，而不是较不必要的冲突规则。系统和方法有利地允许在一段时间内计算进度 框架与规则数量多项式相关，并且比常规方法产生更可预测和更容易理解的时间表。
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公开(公告)号：US07665059B2
公开(公告)日：2010-02-16
申请号：US11448582
申请日：2006-06-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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公开(公告)号：US08572534B2
公开(公告)日：2013-10-29
申请号：US12706470
申请日：2010-02-16
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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公开(公告)号：US20100146468A1
公开(公告)日：2010-06-10
申请号：US12706470
申请日：2010-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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公开(公告)号：US20070288874A1
公开(公告)日：2007-12-13
申请号：US11448582
申请日：2006-06-07
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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