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公开(公告)号：US07665059B2
公开(公告)日：2010-02-16
申请号：US11448582
申请日：2006-06-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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2.发明授权System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread 失效系统存储线程描述符，只有在线程上运行的所有数据准备就绪并且独立于线程的结果命令处理时，才能在存储器中识别多个计算线程之一
公开(公告)号：US5353418A
公开(公告)日：1994-10-04
申请号：US527122
申请日：1990-05-21
申请人： Rishiyur S. Nikhil , Arvind
发明人： Rishiyur S. Nikhil , Arvind
CPC分类号： G06F9/4436
摘要： A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction on set of the at least one processing element is a load instruction that loads global data into local processing element memory that is performed to two phases: a request phase and a response phase. Also included are instructions to fork a thread into two threads and to join two threads into a single thread.
摘要翻译： 多线程并行数据处理系统具有用于处理多个计算线程的至少一个处理元件。 线程由在线程描述符存储中等待处理时存储的线程描述符描述。 线程描述符由指令指针和帧指针组成。 指令指针指向要执行的下一条指令，并且帧指针指向下一条指令将被操作的存储单元的一帧。 包括在至少一个处理元件的集合的指令内的是将全局数据加载到执行到两个阶段的本地处理元件存储器的加载指令：请求阶段和响应阶段。 还包括将线程分成两个线程并将两个线程连接到单个线程的指令。
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公开(公告)号：US20070288874A1
公开(公告)日：2007-12-13
申请号：US11448582
申请日：2006-06-07
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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公开(公告)号：US08572534B2
公开(公告)日：2013-10-29
申请号：US12706470
申请日：2010-02-16
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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公开(公告)号：US20100146468A1
公开(公告)日：2010-06-10
申请号：US12706470
申请日：2010-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F5/06 , G06F17/5031 , G06F17/504
摘要： A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.
摘要翻译： 提供了使用术语重写系统（TRS）的硬件描述语言（HDL），其简化了时钟的处理以及多时钟域电路规范的各个时钟域之间的信令。 提供特定的时钟数据类型用于时钟信号。 使用时钟数据类型和电路规范的其他要求，隐含地处理同一时钟系列的时钟域之间的时钟域交叉。 对于由不同时钟系列的时钟驱动的时钟域之间的时钟域交叉，提供了“硬件方法”和“语言方法”。 “硬件方法”提供明确指定同步器的功能，部分使用TRS规则。 “语言学方法”允许设计人员抽象出同步器的实例，而是根据不同时钟的接口来指定电路规范。
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6.发明授权
公开(公告)号：US5560029A
公开(公告)日：1996-09-24
申请号：US185783
申请日：1994-05-31
CPC分类号： G06F9/4843 , G06F9/3009 , G06F9/3851
摘要： A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the messages from a message queue to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide in a continuation queue an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Alternatively, a single processor may perform the continuation and message processing functions in an interleaved sequence. The data processor creates messages to remote nodes using a global virtual address which is translated before transmission to a node designation and a local virtual address at the remote node.
摘要翻译： PCT No.PCT / US92 / 06150 Sec。 371日期1994年5月31日 102（e）日期1994年5月31日PCT提交1992年7月21日PCT公布。 出版物WO93 / 02414 日期1993年2月4日多处理器系统包括多个处理节点，每个节点处理多个计算线程。 每个节点包括顺序地处理代码块的数据处理器，每个块定义计算线程。 该代码包括发送具有数据值的开始消息以开始新的计算线程的指令。 每个节点还包括用于处理来自系统的相同节点和其他节点的起始消息的同步协处理器。 协处理器处理来自消息队列的消息以将值存储为用于计算线程的操作数，以确定何时接收到计算线程所需的所有操作数，并在连续队列中向数据处理器提供指示线程 可以开始计算。 数据处理器随后非同步地启动计算线程。 或者，单个处理器可以在交错序列中执行连续和消息处理功能。 数据处理器使用在传输到节点指定之前转换的全局虚拟地址和远程节点上的本地虚拟地址来向远程节点创建消息。
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7.发明授权System for learning and applying integrated task and data parallel strategies in dynamic applications 失效在动态应用中学习和应用综合任务和数据并行策略的系统公开(公告)号：US06675189B2
公开(公告)日：2004-01-06
申请号：US09086032
申请日：1998-05-28
IPC分类号： G06F900
CPC分类号： G06N99/005
摘要： A system for learning and applying a task and data parallel strategy to an application that includes at least one task for processing an input data stream to produce an output data stream includes the following components. A controller measuring an execution of the application to generate an action space representing a task and data parallel strategy. A run-time system applying the action space to implement the task and data parallel strategy.
摘要翻译： 一种用于向包括用于处理输入数据流以产生输出数据流的至少一个任务的应用的学习应用任务和数据并行策略的系统包括以下组件。 测量应用程序执行以生成表示任务和数据并行策略的动作空间的控制器。 运行时系统应用动作空间来实现任务和数据并行策略。
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8.发明授权公开(公告)号：US06480876B2
公开(公告)日：2002-11-12
申请号：US09085795
申请日：1998-05-28
IPC分类号： G06F900
CPC分类号： G06F9/5066
摘要： A system for integrating task and data parallelism in a dynamic application that includes at least one task for processing an input data stream to produce an output data stream replaces the at least one task with the following components. A splitter task for partitioning the input data stream into a plurality of data chunks. A plurality of worker tasks for processing subsets of the data chunks, each worker task being an instance of the at least one task, and a joiner task combining the processed data chunks to produce the output data stream.
摘要翻译： 用于在动态应用程序中集成任务和数据并行性的系统，其包括用于处理输入数据流以产生输出数据流的至少一个任务，用下列组件代替至少一个任务。 用于将输入数据流分割成多个数据块的分离器任务。 用于处理数据块的子集的多个工作任务，每个工作任务是至少一个任务的实例，以及组合所处理的数据块以产生输出数据流的加入任务。
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公开(公告)号：US6067604A
公开(公告)日：2000-05-23
申请号：US909405
申请日：1997-08-11
申请人： Umakishore Ramachandran , Robert H. Halstead, Jr. , Christopher F. Joerg , Leonidas Kontothanassis , Rishiyur S. Nikhil , James M. Rehg
发明人： Umakishore Ramachandran , Robert H. Halstead, Jr. , Christopher F. Joerg , Leonidas Kontothanassis , Rishiyur S. Nikhil , James M. Rehg
CPC分类号： G06F9/544 , G06F9/52 , Y10S707/99953 , Y10S707/99957
摘要： In a computer system, a memory is allocated to a plurality of ports. The ports are arranged in a spatial ordering. A plurality of various sized data items are temporally ordered in each of the plurality of ports. Each data item includes a time-stamp to indicate the temporal ordering of the plurality of data items. The plurality of data items are atomically accessed by a plurality of threads using space and time coordinates. The space and time coordinates uniquely identify each of the plurality of data items.
摘要翻译： 在计算机系统中，向多个端口分配存储器。 端口按空间排列排列。 多个不同大小的数据项在多个端口的每一个中被暂时排列。 每个数据项包括指示多个数据项的时间顺序的时间戳。 使用空间和时间坐标由多个线程原子地访问多个数据项。 空间和时间坐标唯一地标识多个数据项中的每一个。
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10.发明授权Pipelined processor with fork, join, and start instructions using tokens to indicate the next instruction for each of multiple threads of execution 失效流水线处理器具有叉，连接和启动指令，使用令牌来指示多个执行线程的下一个指令
公开(公告)号：US5499349A
公开(公告)日：1996-03-12
申请号：US317708
申请日：1994-10-03
申请人： Rishiyur S. Nikhil , Arvind
发明人： Rishiyur S. Nikhil , Arvind
CPC分类号： G06F9/4436
摘要： A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors or tokens which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction set of the at least one processing element is a fork instruction generates two thread descriptors which are added to the current thread descriptors, a start instruction on a first processor sends a message containing a thread descriptor to a second processor, and a join instruction joins two threads by producing a single thread descriptor when both of the joining threads have reached a join instruction.
摘要翻译： 多线程并行数据处理系统具有用于处理多个计算线程的至少一个处理元件。 线程由在线程描述符存储中等待处理时存储的线程描述符或令牌来描述。 线程描述符由指令指针和帧指针组成。 指令指针指向要执行的下一条指令，并且帧指针指向下一条指令将被操作的存储单元的一帧。 包括在至少一个处理元件的指令集中的是，fork指令生成被添加到当前线程描述符的两个线程描述符，第一处理器上的开始指令将包含线程描述符的消息发送到第二处理器，并且 连接指令通过在两个连接线程都到达连接指令时生成单个线程描述符来连接两个线程。
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