公开(公告)号：US20070057708A1

公开(公告)日：2007-03-15

申请号：US11226687

申请日：2005-09-14

申请人： Gregory Uehara ,  Ravikanth Suravarapu

发明人： Gregory Uehara ,  Ravikanth Suravarapu

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891

摘要： The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.

摘要翻译： 延迟锁定环电路包括电荷泵电路，其可以分别响应于上升信号和下降信号的断言而充电和放电。 延迟锁定环电路还包括检测电路，其可以断言指示第一时钟信号的转变的发生的上行信号，并且可以断言指示出现第二时钟信号的转变的向下信号。 延迟锁定环电路还包括延迟电路，其可以提供多个延迟的时钟信号和附加的延迟的时钟信号，每个对应于第一时钟信号的延迟版本。 此外，错误锁定电路可以根据在第一时钟信号的给定时钟周期内是否发生与延迟的时钟信号相关联的预定数量的连续时钟边沿，向检测电路提供复位信号。

公开(公告)号：US07733138B2

公开(公告)日：2010-06-08

申请号：US11226687

申请日：2005-09-14

申请人： Gregory T. Uehara ,  Ravikanth Suravarapu

发明人： Gregory T. Uehara ,  Ravikanth Suravarapu

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891

摘要： The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.

摘要翻译： 延迟锁定环电路包括电荷泵电路，其可以分别响应于上升信号和下降信号的断言而充电和放电。 延迟锁定环电路还包括检测电路，其可以断言指示第一时钟信号的转变的发生的上行信号，并且可以断言指示出现第二时钟信号的转变的向下信号。 延迟锁定环电路还包括延迟电路，其可以提供多个延迟的时钟信号和附加的延迟的时钟信号，每个对应于第一时钟信号的延迟版本。 此外，错误锁定电路可以根据在第一时钟信号的给定时钟周期内是否发生与延迟的时钟信号相关联的预定数量的连续时钟边沿，向检测电路提供复位信号。