公开(公告)号：US20090245446A1

公开(公告)日：2009-10-01

申请号：US12056343

申请日：2008-03-27

Applicant: Tsung-Hsien Hsieh ,  Ray Chih-Jui Peng

Inventor： Tsung-Hsien Hsieh ,  Ray Chih-Jui Peng

IPC: H04L7/04

CPC classification number: G06F13/4059

Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.

Abstract translation: 提供了速率控制的方法和装置。 同步电路控制第一设备和第二设备之间的数据传输。 第一设备以第一数据速率向同步电路输出一组数据分组，并且第二设备以第二数据速率从同步电路提取该组数据分组。 同步电路包括缓冲器，速率计算器和寄存器。 缓冲区通过USB缓冲器绑定到第二个设备的数据包集合。 速率计算器监视缓冲器的占用以估计第二数据速率。 寄存器耦合到速率计算器以存储第二数据速率。 第一设备可以从寄存器访问第二数据速率的估计以更新第一数据速率。

公开(公告)号：US08384436B2

公开(公告)日：2013-02-26

申请号：US12987652

申请日：2011-01-10

Applicant: Ray Chih-Jui Peng

Inventor： Ray Chih-Jui Peng

IPC: H03K10/096 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F1/10 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H03K19/096

Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.

公开(公告)号：US20120176157A1

公开(公告)日：2012-07-12

申请号：US12987652

申请日：2011-01-10

Applicant: Ray Chih-Jui Peng

Inventor： Ray Chih-Jui Peng

IPC: H03K19/096 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F1/10 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H03K19/096

Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.

Abstract translation: 一种方法包括在根时钟下提供包括根时钟和多个级别的集成时钟门（ICG）的第一时钟树。 第一时钟树中的多个级别的ICG被平坦化以在根时钟下产生包括相同电平的多个ICG的第二时钟树。 形成假模块以保留根时钟和多个ICG之间的区域。 假模块包括根时钟作为第一输入，以及耦合到多个ICG的时钟输入的第一多个输出。 使用时钟树合成（CTS）工具在第二时钟树上执行偏斜平衡以产生第三时钟树，其中没有缓冲器被插入到假模块中，并且其中缓冲器被CTS工具在多个ICG下插入 。

公开(公告)号：US07793015B2

公开(公告)日：2010-09-07

申请号：US12056343

申请日：2008-03-27

Applicant: Tsung-Hsien Hsieh ,  Ray Chih-Jui Peng

Inventor： Tsung-Hsien Hsieh ,  Ray Chih-Jui Peng

IPC: G06F13/38

CPC classification number: G06F13/4059

Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.

Abstract translation: 提供了速率控制的方法和装置。 同步电路控制第一设备和第二设备之间的数据传输。 第一设备以第一数据速率向同步电路输出一组数据分组，并且第二设备以第二数据速率从同步电路提取该组数据分组。 同步电路包括缓冲器，速率计算器和寄存器。 缓冲区通过USB缓冲器绑定到第二个设备的数据包集合。 速率计算器监视缓冲器的占用以估计第二数据速率。 寄存器耦合到速率计算器以存储第二数据速率。 第一设备可以从寄存器访问第二数据速率的估计以更新第一数据速率。