公开(公告)号：US06477691B1

公开(公告)日：2002-11-05

申请号：US09542025

申请日：2000-04-03

申请人： Reinaldo A. Bergamashi/Rab ,  Subhrajit Bhattacharya ,  Jean-Marc R. Daveau ,  William R. Lee

发明人： Reinaldo A. Bergamashi/Rab ,  Subhrajit Bhattacharya ,  Jean-Marc R. Daveau ,  William R. Lee

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a “virtual design” and its automatic synthesis into a “real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.

摘要翻译： 在抽象层面描述片上系统的过程和安排。 考虑到创建一个“虚拟设计”及其自动综合成为一个包含图书馆IP块的实际设计以及它们之间所有必需的互连和接口逻辑。与系统相关的复杂性，时间和成本显着降低 因此，可以享受到芯片设计。