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公开(公告)号：US06477691B1
公开(公告)日：2002-11-05
申请号：US09542025
申请日：2000-04-03
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a “virtual design” and its automatic synthesis into a “real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.
摘要翻译： 在抽象层面描述片上系统的过程和安排。 考虑到创建一个“虚拟设计”及其自动综合成为一个包含图书馆IP块的实际设计以及它们之间所有必需的互连和接口逻辑。与系统相关的复杂性，时间和成本显着降低 因此，可以享受到芯片设计。
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公开(公告)号：US07500207B2
公开(公告)日：2009-03-03
申请号：US11354425
申请日：2006-02-15
申请人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
发明人： Subhrajit Bhattacharya , Anthony Correale, Jr. , Nathaniel D. Hieter , Veena S. Pureswaran , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.
摘要翻译： 提供了一种改进的设计电路解决方案。 从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。 获得对目标路径集中的一个或多个节点的影响。 选择一个或多个节点用于使用影响进行改进。 随后，提高了每个选定节点的性能属性。 例如，可以用具有改进的性能属性的实现来替换节点的实现。 可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。 在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。 以这种方式，可以以更有效的方式改善电路。
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3.发明申请Power Gating Techniques Able to Have Data Retention And Variability Immunity Properties 失效电源门控技术能够具有数据保留和可变性抗扰性公开(公告)号：US20080143431A1
公开(公告)日：2008-06-19
申请号：US12034185
申请日：2008-02-20
IPC分类号： G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf−Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
摘要翻译： 电源门控半导体集成电路包括：（1）被电源门控的逻辑电路，所述逻辑电路具有虚拟接地轨; （2）设置在所述虚拟接地轨和地轨之间的脚踏装置，用于减少所述逻辑电路的功耗; 和（3）与所述脚踏装置并联设置的虚拟轨道电压钳，用于限制虚拟接地轨上的电压，虚拟轨电压钳包括至少一个NFET。 总共NFET NFET连接到集成电路的虚拟接地轨，用作虚拟轨道电压钳和脚踏器件。 扫描一定数量的N max-VC NFET，并执行电压钳位的功能，并且剩余的（N-N-N-N-MAX-VC） NFET执行电源门控。 通过根据所制造的集成电路的测试来调整量N max-VC 来实现变异性抗扰度的制造变异性免疫和调谐。
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公开(公告)号：US07516424B2
公开(公告)日：2009-04-07
申请号：US11358456
申请日：2006-02-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.
摘要翻译： 公开了一种用于建模和模拟集成电路的功率分级元件的方法，系统和计算机程序产品。 在对功率宏进行建模时，本发明不将所有逻辑门或元件建模为功率门限，相反，本发明仅将连接到集成开关的锁存器模拟为被加电的宏。 另外，附加到电力宏观的栅栏电路被建模为包括额外的控制信号，以将强力宏观的电力状态强制进入栅栏电路。
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5.发明授权Verification of scheduling in the presence of loops using uninterpreted symbolic simulation 有权使用未解释的符号仿真验证在存在循环的情况下的调度公开(公告)号：US07383166B2
公开(公告)日：2008-06-03
申请号：US10756303
申请日：2004-01-14
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.
摘要翻译： 一种检查电路调度的正确性的方法，其中从行为描述获得电路的调度。 该方法包括提取循环不变量以在存在循环时确定足够的非循环线程集合，执行符号仿真以提取上述循环不变量，以及证明非循环线程的等价性。 还公开了结合根据本发明的验证和正确性检查技术的系统，计算机系统和计算机程序产品。
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公开(公告)号：US07469401B2
公开(公告)日：2008-12-23
申请号：US11359229
申请日：2006-02-22
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.
摘要翻译： 掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。 提供了一种方法，包括：在具有可重复使用的掩模组的预定位置处将一组部件芯片打印到管芯上; 提供自定义阻挡掩模，其包括与裸片上的部件芯位置对应的不透明区域; 将自定义阻止掩码与通用数组类型的单元格掩码叠加以形成叠加的掩码; 并且使用叠加的掩模将通用阵列类型的单元格打印到管芯上，除了组件核心所在的预定位置之外。
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7.发明授权Power gating techniques able to have data retention and variability immunity properties 有权电源门控技术能够具有数据保留和可变性的抗扰性公开(公告)号：US07420388B2
公开(公告)日：2008-09-02
申请号：US11498009
申请日：2006-08-01
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
摘要翻译： 电源门控半导体集成电路包括：（1）被电源门控的逻辑电路，所述逻辑电路具有虚拟接地轨; （2）设置在所述虚拟接地轨和地轨之间的脚踏装置，用于减少所述逻辑电路的功耗; 和（3）与所述脚踏装置并联设置的虚拟轨道电压钳，用于限制虚拟接地轨上的电压，虚拟轨电压钳包括至少一个NFET。 总共NFET NFET连接到集成电路的虚拟接地轨，用作虚拟轨道电压钳和脚踏器件。 扫描一定数量的N max-VC NFET，并执行电压钳位的功能，并且剩余的（N-N-N-N-MAX-VC） NFET执行电源门控。 通过根据所制造的集成电路的测试来调整量N max-VC 来实现变异性抗扰度的制造变异性免疫和调谐。
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公开(公告)号：US20070196958A1
公开(公告)日：2007-08-23
申请号：US11359229
申请日：2006-02-22
IPC分类号： H01L21/82 , H01L21/331
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.
摘要翻译： 掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。 提供了一种方法，包括：在具有可重复使用的掩模组的预定位置处将一组部件芯片打印到管芯上; 提供自定义阻挡掩模，其包括与裸片上的部件芯位置对应的不透明区域; 将自定义阻止掩码与通用数组类型的单元格掩码叠加以形成叠加的掩码; 并且使用叠加的掩模将通用阵列类型的单元格打印到管芯上，除了组件核心所在的预定位置之外。
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9.发明申请Power gating techniques able to have data retention and variability immunity properties 有权电源门控技术能够具有数据保留和可变性的抗扰性公开(公告)号：US20060091913A1
公开(公告)日：2006-05-04
申请号：US10978067
申请日：2004-10-28
IPC分类号： H03K19/096
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf−Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
摘要翻译： 电源门控半导体集成电路包括：（1）被电源门控的逻辑电路，所述逻辑电路具有虚拟接地轨; （2）设置在所述虚拟接地轨和地轨之间的脚踏装置，用于减少所述逻辑电路的功耗; 和（3）与所述脚踏装置并联设置的虚拟轨道电压钳，用于限制虚拟接地轨上的电压，虚拟轨电压钳包括至少一个NFET。 总共NFET NFET连接到集成电路的虚拟接地轨，用作虚拟轨道电压钳和脚踏器件。 扫描一定数量的N max-VC NFET，并执行电压钳位的功能，并且剩余的（N-N-N-N-MAX-VC） NFET执行电源门控。 通过根据所制造的集成电路的测试来调整量N max-VC 来实现变异性抗扰度的制造变异性免疫和调谐。
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公开(公告)号：US07870531B2
公开(公告)日：2011-01-11
申请号：US12117841
申请日：2008-05-09
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.
摘要翻译： 掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。 提供一种系统，其包括具有对应于多个硬知识产权（IP）组件的多个可重复使用的掩模的掩模组; 通用数组类型的单元格掩码; 以及自定义阻挡掩模，其包括与印刷在管芯上的一组IP部件位置对应的阻挡区域。
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