公开(公告)号：US5359547A

公开(公告)日：1994-10-25

申请号：US904784

申请日：1992-06-26

申请人： William H. Cummins ,  R. Stephen Polzin ,  Richard Heye

发明人： William H. Cummins ,  R. Stephen Polzin ,  Richard Heye

IPC分类号： G01R31/319 ,  G06F11/267 ,  G06F11/22

CPC分类号： G06F11/2236 ,  G01R31/31917

摘要： A method and apparatus for testing complex processor-based computer modules and their associated computer systems by allowing the normal initialization path between a memory component storing code utilized during initialization and the processor to be interrupted and test code from an external test system to be substituted for initialization code. Following initialization, a two-way communication link between the processor and the test system is created to allow interactive testing and status reporting. The testing method and apparatus maximizes the likelihood of precisely identifying defects on the module under test.

摘要翻译： 一种用于通过在存储组件存储初始化期间使用的代码和处理器被中断的存储器组件和来自外部测试系统的测试代码之间允许正常的初始化路径来测试复杂的基于处理器的计算机模块及其相关联的计算机系统的方法和装置， 初始化代码。 初始化后，创建处理器和测试系统之间的双向通信链路，以便进行交互式测试和状态报告。 测试方法和设备最大限度地提高了在被测模块上精确识别缺陷的可能性。

公开(公告)号：US5430888A

公开(公告)日：1995-07-04

申请号：US143509

申请日：1993-10-26

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

摘要翻译： 用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。 流水线包括支持多个未完成读请求未命中的缓冲区。 来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。 然后可以用所请求的数据填充高速缓存存储器。 在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

公开(公告)号：US5148536A

公开(公告)日：1992-09-15

申请号：US224483

申请日：1988-07-25

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.