公开(公告)号：US4459656A

公开(公告)日：1984-07-10

申请号：US307565

申请日：1981-10-01

申请人： Richard P. Wilder, Jr.

发明人： Richard P. Wilder, Jr.

IPC分类号： G06F11/34 ,  G06F11/00

CPC分类号： G06F11/348 ,  G06F11/3419 ,  G06F11/349 ,  G06F2201/885

摘要： A hardware monitor interface unit (HMIU) is coupled to a data processing system. Programmable hit matrices (PHM's) in the HMIU store information which is compared with information from the data processing system. The PHM's generate "hit" signals indicating comparison. These "hit" signals are received by monitors coupled to the HMIU which are used to compile the data processing system performance data. Appartus in the HMIU generates clocking signals enabling the information to be received by the HMIU and generates strobing signals to be used for timing the "hit" signals and other control signals received by the monitors.

摘要翻译： 硬件监视器接口单元（HMIU）耦合到数据处理系统。 HMIU存储信息中的可编程命中矩阵（PHM），与来自数据处理系统的信息进行比较。 PHM产生指示比较的“命中”信号。 这些“击中”信号由耦合到HMIU的监视器接收，用于编译数据处理系统性能数据。 HMIU中的Appartus产生时钟信号，使得HMIU可以接收信息，并产生选通信号，用于定时监视器接收的“命中”信号和其他控制信号。

公开(公告)号：US4438490A

公开(公告)日：1984-03-20

申请号：US307564

申请日：1981-10-01

申请人： Richard P. Wilder, Jr.

发明人： Richard P. Wilder, Jr.

IPC分类号： G06F11/34 ,  G06F11/30 ,  G06F1/04

CPC分类号： G06F11/348 ,  G06F11/349

摘要： A monitor interface unit couples a monitor to a data processing system which includes a central processing unit (CPU). The monitor generates data for determining the performance of the data processing unit. The monitor interface unit includes apparatus for stopping the CPU clock during a particular CPU operation and then slowing down the CPU clock rate.

摘要翻译： 监视器接口单元将监视器耦合到包括中央处理单元（CPU）的数据处理系统。 监视器生成用于确定数据处理单元的性能的数据。 监视器接口单元包括在特定CPU操作期间停止CPU时钟，然后使CPU时钟速率变慢的装置。

公开(公告)号：US4521849A

公开(公告)日：1985-06-04

申请号：US307566

申请日：1981-10-01

申请人： Richard P. Wilder, Jr.

发明人： Richard P. Wilder, Jr.

IPC分类号： G06F9/00 ,  G06F11/34 ,  G06F7/00

CPC分类号： G06F11/348 ,  G06F11/349

摘要： A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE's in locations addressed by predetermined portions of the information and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor to collect statistical data.

摘要翻译： 硬件监视接口单元（HMIU）耦合到数据处理单元并接收在数据处理单元的子系统之间传送的所有信息。 可编程命中矩阵（PHM）包括用于接收信息的输入锁存器，用于在由信息的预定部分寻址的位置中存储二进制ONE的存储器电路，以及用于存储从存储器电路读取的二进制“1”或“命中”信号的输出锁存器。 “命中”信号被插入到监视器中的逻辑电路和计数器中以收集统计数据。

公开(公告)号：US4458309A

公开(公告)日：1984-07-03

申请号：US307569

申请日：1981-10-01

申请人： Richard P. Wilder, Jr.

发明人： Richard P. Wilder, Jr.

IPC分类号： G06F11/34 ,  G06F11/30

CPC分类号： G06F11/348 ,  G06F11/349 ,  G06F11/3495

摘要： A data processing system includes a number of subsystems, all coupled in common to a system bus. Also coupled to the system bus is a hardware monitor interface unit (HMIU) for receiving all information transferred between subsystems. The HMIU includes programmable hit matrices (PHM's). The PHM's include memory circuits which generate "hit" signals when predetermined information addresses the memory circuits. The "hit" signals or binary ONE's are loaded into the memory circuits during a load mode during which system bus information specifically addressing the HMIU is received on two system bus cycles for each address location of the memory circuit. The data bus contains the memory circuit address during the first system bus cycle and the data during the second data bus cycle. An address bus signal identifies the cycle.

摘要翻译： 数据处理系统包括多个子系统，所有子系统都共同地耦合到系统总线。 还耦合到系统总线的是用于接收在子系统之间传送的所有信息的硬件监视器接口单元（HMIU）。 HMIU包括可编程命中矩阵（PHM）。 PHM包括当预定信息寻址存储器电路时产生“命中”信号的存储器电路。 在负载模式期间，“命中”信号或二进制ONE被加载到存储器电路中，在负载模式期间，在存储器电路的每个地址位置的两个系统总线周期上接收专门寻址HMIU的系统总线信息。 数据总线包含第一个系统总线周期期间的存储器电路地址和第二个数据总线周期期间的数据。 地址总线信号标识周期。