公开(公告)号：US08438548B2

公开(公告)日：2013-05-07

申请号：US13021609

申请日：2011-02-04

申请人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

发明人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

IPC分类号： G06F9/455

CPC分类号： G06F9/3808 ,  G06F9/3812

摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

摘要翻译： 在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。 响应于检测，将目标指令的副本存储在主机存储器中。 响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。 此外，响应于基于比较的不匹配，主机指令被禁用。

公开(公告)号：US20080313440A1

公开(公告)日：2008-12-18

申请号：US12177836

申请日：2008-07-22

申请人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

发明人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

IPC分类号： G06F9/315

CPC分类号： G06F9/3808 ,  G06F9/3812

摘要： A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

摘要翻译： 将指令从目标指令集转换为主机指令集的方法。 在一个实施例中，多个第一目标指令被转换成多个第一主机指令。 在翻译之后，确定多个第一目标指令是否已改变。 如果确定减慢了计算机系统的操作，则存储第二多个目标指令的副本并与多个第一目标指令进行比较。 在比较之后，如果存在不匹配，则多个第一主机指令被无效。 根据一个实施例，当确定指示页面包含对多个第一目标指令的至少一个改变时，开始存储，比较和无效。 在一个实施例中，确定是通过检查与多个第一目标指令的存储器位置相关联的比特指示符。