摘要:
In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
摘要:
A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.
摘要:
A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.
摘要:
In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
摘要:
In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
摘要:
A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.
摘要:
In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes. The method includes testing whether the target instructions at a memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location and determining whether the testing is slowing the operation of the computer system. If the testing is slowing the operation of the computer system, a checking process initiated, which includes storing a copy of the sequence of target instructions and comparing the copy with the sequence of target instructions.
摘要:
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
摘要:
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
摘要:
Methods and systems that allow recovery of the program counter or instruction pointer for a target (non-native) instruction that is translated into a host (native) instruction, and that allow recovery of other information about the translator or the target system state, are described. The program counter or instruction pointer can be recovered, for example, after an exception has been processed or incident to a rollback operation.