公开(公告)号：US06920625B2

公开(公告)日：2005-07-19

申请号：US10422666

申请日：2003-04-24

申请人： Robert Benjamin Gass

发明人： Robert Benjamin Gass

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An apparatus and method for optimum transparent latch placement in a macro design are provided. With the apparatus and method, a tree graph data structure is generated to represent the design wherein nodes of the tree graph data structure represent macros of the design. Each node of the tree graph data structure is augmented to include a maximum latch number and a clocking domain. Any leaf nodes of the tree graph data structure that cannot have latches placed in them, but have latch placement requirements, have their latch placement requirements added to their parent node if their parent node has more than one child node. The tree graph data structure is traversed to find the most timing critical nodes with timing requirements that have not been satisfied. A most timing critical path of these paths is identified. Intermediate nodes along this path are examined to determine if there are any latch placement requirements that must be met for the nodes. If these nodes have associated latch placement requirements, the requirements are satisfied first. Then latch placement along the critical path is performed in accordance with a one or more project specific placement rules.

摘要翻译： 提供了一种用于在宏观设计中实现最佳透明锁定放置的装置和方法。 利用设备和方法，生成树形图数据结构以表示其中树形图数据结构的节点表示设计宏的设计。 增加了树形图数据结构的每个节点以包括最大锁存数和时钟域。 如果树形图数据结构的父节点具有多个子节点，则树形图数据结构的任何叶节点不能将锁存器放置在其中，但具有锁存放置要求，则将其锁存放置要求添加到其父节点。 遍历树形图数据结构以找到具有尚未满足的时序要求的大多数时序关键节点。 确定这些路径的最时间关键路径。 检查沿该路径的中间节点，以确定是否存在节点必须满足的任何锁定放置要求。 如果这些节点具有相关的锁定放置要求，则首先满足要求。 然后根据一个或多个项目特定的放置规则执行沿关键路径的锁定放置。

公开(公告)号：US20100050031A1

公开(公告)日：2010-02-25

申请号：US12195641

申请日：2008-08-21

申请人： Robert Benjamin Gass ,  Phillip G. Williams

发明人： Robert Benjamin Gass ,  Phillip G. Williams

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/3187

摘要： An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

摘要翻译： LBIST从伪随机模式生成器捕获伪随机值。 接下来，LBIST通过将捕获的伪随机值输入到未定义的逻辑路径来稳定未定义的逻辑路径。 反过来，LBIST测试依赖于稳定的未定义逻辑路径的一个或多个定时信号转换。

公开(公告)号：US07934135B2

公开(公告)日：2011-04-26

申请号：US12195641

申请日：2008-08-21

申请人： Robert Benjamin Gass ,  Phillip G. Williams

发明人： Robert Benjamin Gass ,  Phillip G. Williams

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/3187

摘要： An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

摘要翻译： LBIST从伪随机模式生成器捕获伪随机值。 接下来，LBIST通过将捕获的伪随机值输入到未定义的逻辑路径来稳定未定义的逻辑路径。 反过来，LBIST测试依赖于稳定的未定义逻辑路径的一个或多个定时信号转换。

公开(公告)号：US07234088B2

公开(公告)日：2007-06-19

申请号：US10651168

申请日：2003-08-28

申请人： Robert Benjamin Gass

发明人： Robert Benjamin Gass

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318577

摘要： The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal transitions consistent with the normal operating speed of the device. This occurs even when a normal signal transition would not otherwise occur since the multi-cycle bus normally requires a plurality of clock pulses to create such signal transition. The logical states of master and slave clocks associated with test scan logic are used to automatically cause the output of a scan latch to invert its output or switch from its previous state at each rising edge of the slave clock that is not preceded by a master or scan clock. This ensures transitions will appear at the output of the latch consistent with the operating clock speed of the slave clock, and these transitions are detected during an AC test of the device to determine the maximum operation frequency of the device even when the device contains an internal multi-cycle bus.

摘要翻译： 本发明涉及用于对电子设备进行自检的改进方法，系统和装置。 在多周期总线中使用的扫描锁存器被唯一地操作以产生与设备的正常操作速度一致的信号转换。 即使当由于多周期总线通常需要多个时钟脉冲来产生这种信号转换时，也不会发生正常信号转换，所以这种情况发生。 与测试扫描逻辑相关联的主时钟和从时钟的逻辑状态用于自动导致扫描锁存器的输出将其输出或从先前状态切换到从时钟的每个上升沿，其前面不会有主器件或 扫描时钟。 这确保了与从时钟的工作时钟速度一致的锁存器输出上的转换将出现在器件的交流测试中，即使在器件包含内部时也会检测器件的最大工作频率 多循环总线