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1.发明授权Private cache miss and access management in a multiprocessor system with shared memory 失效具有共享内存的多处理器系统中的专用缓存未命中和访问管理
公开(公告)号：US5829029A
公开(公告)日：1998-10-27
申请号：US769682
申请日：1996-12-18
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F12/0811 , G06F12/0831 , G06F12/084
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓存存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器 以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识 组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于 块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。
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2.发明授权Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache 失效在使用个别中央处理器单元和共享缓存的专用高速缓存的多处理器计算机系统中的信息块传输管理
公开(公告)号：US6006309A
公开(公告)日：1999-12-21
申请号：US768552
申请日：1996-12-18
CPC分类号： G06F12/0811 , G06F12/0859
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和包括一对半块操作数缓冲器的高速缓存控制器，每个缓存器被分成四个块段。 操作数缓冲器组被耦合以在输入多路复用器的控制下选择性地在四分之一块区段中从CPU总线接收所请求的信息块，并且还被耦合以在输出多路复用器的控制下将接收的四分之一块段 CPU并接收到高速缓冲存储器的完整块。
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3.发明授权Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment 有权在多处理器写入高速缓存环境中等同的访问来防止门字优势公开(公告)号：US06970977B2
公开(公告)日：2005-11-29
申请号：US10403703
申请日：2003-03-31
CPC分类号： G06F12/084
摘要： In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.
摘要翻译： 一种多处理器写入高速缓存数据处理系统，包括：存储器; 至少第一和第二共享高速缓存; 耦合存储器和共享缓存的系统总线; 至少一个处理器具有分别耦合到每个共享高速缓存的专用高速缓存; 方法和装置，用于防止存储在存储器中的门字的所有权，其控制对在处理器中运行的进程共享的共同代码/数据的访问，通过该处理器，由给定处理器通过执行连续的交换操作来获得门字的读取副本 内存和给定处理器的共享缓存，以及给定的处理器的共享缓存和专用缓存。 如果门字被发现是OPEN，则由给定的处理器关闭，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，并且共享高速缓存和存储器将门字CLOSEd写入存储器，使得给定的处理器获得 独占访问受管制的通用代码/数据。 当给定的处理器完成使用通用代码/数据时，它将门字OPEN写入其专用缓存，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，共享高速缓存和存储器将门槛OPEN写入存储器 。
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4.发明授权Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data 失效多处理器计算机系统，包括用于动态分配可变数据的所有权的方法和装置
公开(公告)号：US5963973A
公开(公告)日：1999-10-05
申请号：US796309
申请日：1997-02-07
CPC分类号： G06F12/0833
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：处理器目录，用于存储标识驻留在高速缓冲存储器中的信息块的识别字，并且包括指示本地CPU在块上的写许可权限的状态字段;输出缓冲器 用于存储驻留在CPU不具有的高速缓冲存储器中的块的识别字，并且寻求写许可，并且用于选择性地将标识字和无效命令发送到CPU总线上;输入缓冲器，用于存储所有最近的识别字 响应于比较器感测比较条件（通常指示另一个CPU对另一个CPU的写入许可的请求），比较器用于将输出缓冲器中的识别字与输入缓冲器和控制逻辑中的标识进行比较 相同的块，本地CPU也要求写入许可），用于aborti 纳入本地CPU的写许可请求并建立重试过程。
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