公开(公告)号：US09146600B2

公开(公告)日：2015-09-29

申请号：US11870562

申请日：2007-10-11

申请人： Robert J. P. Nychka ,  Laurent Geffroy ,  Sonu Arora ,  Vipin Verma

发明人： Robert J. P. Nychka ,  Laurent Geffroy ,  Sonu Arora ,  Vipin Verma

IPC分类号： G06F1/32 ,  G11C11/4074

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G11C11/4074

摘要： Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

摘要翻译： 本文描述了用于计算机系统内部件的离散功率控制的系统和方法。 一些说明性实施例包括系统，其包括具有多个组件（可配置为在一个或多个功率电平下操作）的子系统，包括多个位（每个唯一地与一个位相关联的多个位组合）的控制寄存器 多个组件）以及功率控制器，其耦合到并且可配置为使多个组件在一个或多个功率水平下操作。 功率控制器断言发送到子系统的信号，命令子系统转换到第一功率电平。 与控制寄存器的断言位相关联的多个部件中的第一个在与功率控制器指示的第一功率电平的功耗水平不同的第二功率电平下工作。

公开(公告)号：US20080091965A1

公开(公告)日：2008-04-17

申请号：US11870562

申请日：2007-10-11

申请人： Robert J. P. NYCHKA ,  Laurent GEFFROY ,  Sonu ARORA ,  Vipin VERMA

发明人： Robert J. P. NYCHKA ,  Laurent GEFFROY ,  Sonu ARORA ,  Vipin VERMA

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G11C11/4074

摘要： Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

摘要翻译： 本文描述了用于计算机系统内部件的离散功率控制的系统和方法。 一些说明性实施例包括系统，其包括具有多个组件（可配置为以一个或多个功率电平操作）的子系统，包括多个位（每个唯一地与一个位相关联的多个位组合）的控制寄存器 多个组件）以及功率控制器，其耦合到并且可配置为使多个组件在一个或多个功率水平下操作。 功率控制器断言发送到子系统的信号，命令子系统转换到第一功率电平。 与控制寄存器的断言位相关联的多个部件中的第一个在与功率控制器指示的第一功率电平的功耗水平不同的第二功率电平下工作。

公开(公告)号：US07139854B2

公开(公告)日：2006-11-21

申请号：US10458572

申请日：2003-06-10

申请人： Jonathan Y. Zhang ,  Robert J. P. Nychka ,  Eric L. P. Badi

发明人： Jonathan Y. Zhang ,  Robert J. P. Nychka ,  Eric L. P. Badi

IPC分类号： G06F13/00

CPC分类号： G06F13/37

摘要： Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.

摘要翻译： 本文公开的装置和方法在总线架构上提供减少的总线事务等待时间，该总线架构包括耦合到多个从机的至少一个主机。 如本文所公开的，设备（例如，从设备）可以包括总线逻辑和耦合到总线逻辑的主机逻辑。 总线逻辑可以获得允许主机逻辑经由总线完成由总线逻辑接收到的事务的串行化令牌。 此外，总线逻辑可以保持串行化令牌来完成至少一个其他事务。