公开(公告)号：US20050246579A1

公开(公告)日：2005-11-03

申请号：US11150796

申请日：2005-06-10

申请人： Robert Rust ,  Tammy Van De Graaff ,  Barry Oldfield

发明人： Robert Rust ,  Tammy Van De Graaff ,  Barry Oldfield

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F11/20 ,  G06F12/16 ,  G06F13/14

CPC分类号： G06F11/2089 ,  G06F3/0601 ,  G06F11/2007 ,  G06F11/201 ,  G06F11/2056 ,  G06F11/2092 ,  G06F2003/0692

摘要： A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.

摘要翻译： RAID磁盘阵列内的控制器互连结构可实现阵列内的多个控制器对之间的连续低延迟/高带宽通信。 镜像总线在执行镜像记忆操作的镜像控制器之间承载高速镜像流量。 环路总线在控制器回路中连接在一起的控制器对之间携带处理器间通信和其他流量。 互连结构的优点包括在各种故障和修复条件下支持持续控制器通信和在线磁盘阵列操作的能力，否则可能导致磁盘阵列无法使用。 此外，控制器互连结构提供了容易扩展磁盘阵列内的控制器的数量，因为阵列继续按比例放大以满足来自用户主机系统的增加的存储需求。

公开(公告)号：US5517601A

公开(公告)日：1996-05-14

申请号：US316162

申请日：1994-09-30

申请人： Robert Rust ,  Eugene A. Roylance

发明人： Robert Rust ,  Eugene A. Roylance

IPC分类号： B41J2/485 ,  G06K7/14 ,  G06T11/40 ,  G09G5/24 ,  G09G5/36 ,  G06K7/10

CPC分类号： G06K7/143 ,  G06K7/14

摘要： An apparatus derives data to enable a fill action during operation of a print device along a scan line. The apparatus includes a processor which determines, for each of a sequence of contours of a glyph, point of intersection values between a scan line and the contours. The sequential point of intersection values indicate OFF-to-ON and ON-to-OFF transitions required of the print device. Sequential OFF-to-ON and ON-to-OFF transitions comprise a transition pair. The apparatus includes a memory comprising 2N storage positions for storage of N transition pairs. Comparator circuitry is coupled in parallel to the 2N storage positions. A controller operates the comparator circuitry to determine an order of all OFF-to-ON point of intersection values and an order of all ON-to-OFF point of intersection values in the 2N storage positions. Switch circuitry is responsive to the determined order of OFF-to-ON point of intersection values to re-order the OFF-to-ON point of intersection values in the 2N storage positions and is further responsive to the determined order of the ON-to-OFF point of intersection values to re-order the ON-to-OFF point intersection values in the 2N storage positions. Overlap regions are determined and transition pairs to be arranged so that overlap regions are ignored.

摘要翻译： 一个装置导出数据，以便在沿着扫描线的打印装置的操作期间执行填充动作。 该装置包括一个处理器，对于一个字形的轮廓序列中的每一个，确定扫描线和轮廓之间的交点值。 顺序交叉点值表示打印设备所需的OFF到ON和ON到OFF转换。 顺序关断到ON和ON到OFF转换包括转换对。 该装置包括存储N个存储位置以存储N个转换对的存储器。 比较器电路并联耦合到2N个存储位置。 控制器操作比较器电路以确定所有OFF到ON交点交点值的顺序和2N个存储位置中所有ON到OFF交点值的顺序。 开关电路响应于所确定的OFF到ON点交点值的顺序来重新排列2N个存储位置中的OFF到ON点的交点值，并且进一步响应于所确定的ON-到 -OFF点的交点值重新排列2N个存储位置中的ON到OFF点交点值。 重叠区域被确定，并且转换对被布置成忽略重叠区域。

公开(公告)号：US5574953A

公开(公告)日：1996-11-12

申请号：US293229

申请日：1994-08-19

申请人： Robert Rust ,  Roger L. Pennington

发明人： Robert Rust ,  Roger L. Pennington

IPC分类号： G06F5/00 ,  G06F12/02 ,  G06T9/00 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46

CPC分类号： H03M7/30 ,  G06F12/0223 ,  G06F12/023 ,  G06T9/005 ,  H03M7/4006 ,  G06F2212/401

摘要： A data compression and decompression method for storing compressed data in non-contiguous memory. As the data is compressed and stored in memory, any non-contiguous segments are properly marked. Such marking requires that the last location contains a pointer to the next memory location used. Just prior to the pointer a special "LINK" code is stored. Thus, when the compressor completes its job, the non-contiguous memory is logically linked together. To decompress the compressed data, a code of the compressed data is retrieved from the non-contiguous memory. If the code is a link code, then an address pointer to the next location in memory where the next compressed data is stored is retrieved from memory. If, in the alternative, the code in not a link code then the code is decompressed.

摘要翻译： 用于将压缩数据存储在非连续存储器中的数据压缩和解压缩方法。 当数据被压缩并存储在存储器中时，任何不连续的段被正确标记。 这种标记要求最后一个位置包含指向所使用的下一个存储位置的指针。 在指针之前，存储一个特殊的“LINK”代码。 因此，当压缩机完成其工作时，不连续的存储器被逻辑地链接在一起。 为了解压缩压缩数据，从非连续存储器检索压缩数据的代码。 如果代码是链接代码，则从内存中检索存储器中存储下一个压缩数据的下一个位置的地址指针。 如果代替的代码不是链接代码，那么代码就被解压缩了。

公开(公告)号：US5442664A

公开(公告)日：1995-08-15

申请号：US171314

申请日：1993-12-20

申请人： Robert Rust ,  Phillip R. Luque ,  Derek L. Knee

发明人： Robert Rust ,  Phillip R. Luque ,  Derek L. Knee

IPC分类号： H03K5/13 ,  H03K7/06 ,  H03K9/06

CPC分类号： H03K7/06

摘要： A modulator for a clock pulse generator receives clock pulses from a clock pulse source, which clock pulses exhibit a reference phase. Delay circuitry is connected to the clock pulse source and includes n tap connections, each connection providing a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer is connected to each of the n tap connections and provides an output manifesting the clock pulses. A selector circuit controls the multiplexer to sequentially connect any sequence of different ones of the n tap connections to the multiplexer's output, whereby the output manifests a series of clock pulses which have different phase displacements from the reference phase.

摘要翻译： 用于时钟脉冲发生器的调制器从时钟脉冲源接收时钟脉冲，该时钟脉冲表现出参考相位。 延迟电路连接到时钟脉冲源，并包括n个抽头连接，每个连接提供延时与参考相位不同的相位延迟的时钟脉冲。 多路复用器连接到n抽头连接中的每一个，并提供表示时钟脉冲的输出。 选择器电路控制多路复用器将n个抽头连接中的任何序列顺序地连接到多路复用器的输出端，从而输出表现出与参考相位具有不同相位位移的一系列时钟脉冲。

公开(公告)号：US20050120190A1

公开(公告)日：2005-06-02

申请号：US11023091

申请日：2004-12-24

申请人： Robert Rust ,  Eugene Cohen ,  Scott McLean

发明人： Robert Rust ,  Eugene Cohen ,  Scott McLean

IPC分类号： G06F3/06 ,  G06F9/46 ,  G06F11/20 ,  G06F15/00 ,  G06F15/16 ,  G06F15/76

CPC分类号： G06F3/065 ,  G06F3/0617 ,  G06F3/0689 ,  G06F9/544 ,  G06F11/2089 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.