公开(公告)号：US20050004127A1

公开(公告)日：2005-01-06

申请号：US10896961

申请日：2004-07-23

申请人： Peter Strehlke ,  Peter Droescher ,  Ulrich Buehmann ,  Norbert Schmees ,  Peter Muhn ,  Holger Hess-Stumpp ,  Roland Kuhne ,  Eckhard Guenther ,  Emmanuel Polymeropoulos ,  Antonius Ter Laak

发明人： Peter Strehlke ,  Peter Droescher ,  Ulrich Buehmann ,  Norbert Schmees ,  Peter Muhn ,  Holger Hess-Stumpp ,  Roland Kuhne ,  Eckhard Guenther ,  Emmanuel Polymeropoulos ,  Antonius Ter Laak

IPC分类号： A61K31/47 ,  A61P5/02 ,  C07D215/56 ,  C07D237/32 ,  C07D401/04 ,  C07D401/12 ,  C07D409/04 ,  A61K31/502 ,  A61K31/517

CPC分类号： C07D401/04 ,  A61K31/47 ,  C07D215/56 ,  C07D237/32 ,  C07D401/12 ,  C07D409/04

摘要： The invention relates to new quinoline, isoquinoline and phthalazine derivatives as antagonists of the gonadotropin-releasing hormone.

摘要翻译： 本发明涉及作为促性腺激素释放激素拮抗剂的新喹啉，异喹啉和酞嗪衍生物。

公开(公告)号：US4558455A

公开(公告)日：1985-12-10

申请号：US535128

申请日：1983-09-23

申请人： Gabriel Epenoy ,  Roland Kuhne

发明人： Gabriel Epenoy ,  Roland Kuhne

IPC分类号： H04L1/00 ,  H04L5/22 ,  H04L25/05 ,  H04J3/06

CPC分类号： H04L5/22 ,  H04L1/0083 ,  H04L25/05

摘要： In the modem based data transmission system the transmitting section provides a bit from each terminal (DTE) to be stored into a transmission buffer register (BX) under the control of an external clock signal derived from a modem internal transmission clock signal. The contents of the transmission buffer register is transferred into a transmission shift register and then transferred toward the modem through a formatting logic circuit wherein so-called stuffing bits and synchronization or flag characters are being inserted. Opposite operations are performed in the receiving section of the data transmission system.

摘要翻译： 在基于调制解调器的数据传输系统中，发射部分在来自调制解调器内部传输时钟信号的外部时钟信号的控制下，从每个终端（DTE）提供要存储到传输缓冲寄存器（BX）中的位。 发送缓冲寄存器的内容被传送到发送移位寄存器，然后通过格式化逻辑电路向调制解调器传送，其中插入所谓的填充位和同步或标志字符。 在数据传输系统的接收部分执行相反的操作。

公开(公告)号：US4648102A

公开(公告)日：1987-03-03

申请号：US586475

申请日：1984-03-05

申请人： Vladimir Riso ,  Roland Kuhne

发明人： Vladimir Riso ,  Roland Kuhne

IPC分类号： G06F13/36 ,  G06F13/42 ,  H04L25/24 ,  H04L7/00 ,  G06F13/00

CPC分类号： G06F13/4291 ,  G06F13/36 ,  H04L25/242

摘要： A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines.The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7.The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.

摘要翻译： 一种用于数据处理系统的总线接口装置，其中2M个单元互连，并且通过总线上的交换信息位至少包括M行。 该装置包括与总线的每个相应线路（D0-D7）相关联的接收电路，并且包括两个触发器40和41，它们在时钟的上行和下行转换中呈现输入线上的电压电平 信号（CLK1），并在该信号的下行和上行转换中恢复。 当通过总线接收的位被编码为NRZ代码时，使用等于时钟信号的一半周期的位周期，或者电路47在其输出端提供在D0-D7上接收的重新同步的输入位串。 2M单元分为两组，每组中的单元在第二个时钟信号（CLK2）的任一阶段请求访问总线。 当总线空闲时，触发器48和49提供对由相关联的单元制造的访问总线的请求的指示。

公开(公告)号：US4202039A

公开(公告)日：1980-05-06

申请号：US964316

申请日：1978-11-29

申请人： Gabriel I. Epenoy ,  Roland Kuhne ,  Bernard Laurent ,  Philippe E. Thirion

发明人： Gabriel I. Epenoy ,  Roland Kuhne ,  Bernard Laurent ,  Philippe E. Thirion

IPC分类号： G06F7/53 ,  G06F7/48 ,  G06F7/506 ,  G06F7/508 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544 ,  G06F17/16 ,  G06F7/52

CPC分类号： G06F7/5443 ,  G06F7/4812

摘要： A specialized processor capable of computing a sum of products S=.SIGMA..+-.Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j=.sqroot.-1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.

摘要翻译： 一种专门的处理器，能够计算乘积之和S = SIGMA +/- Pi，其中每个乘积Pi是两个n位复数操作数Ai + j Bi，乘法器和Ci + j Di，被乘数的乘积，其中j = 2ROOT -1。 处理器包括指令存储装置，用于解码从所述存储器读出并用于控制处理器的操作的指令的装置，数据存储器和具有两个乘法累加器装置和多个用于存储操作数Ai的缓冲器的乘法和累加单元 ，Bi，Ci和Di顺序读出数据存储。 乘法器的实部Ai和虚部Bi分别应用于乘法器 - 累加器器件的乘法器输入，并且被乘数的实部Ci被应用于乘法器 - 累加器器件的乘法器输入，其同时计算 产品Ai Ci和Bi Ci。 被乘数的虚部Di然后被施加到乘法器 - 累加器装置的乘法器输入。 其中第一个然后计算产品Bi Di并将其添加到产品Ai Ci，而第二个设备计算乘积Ai Di并将其添加到产品Bi Ci以同时提供产品Pi的实部和虚部 。