公开(公告)号：US5960457A

公开(公告)日：1999-09-28

申请号：US846651

申请日：1997-05-01

申请人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

发明人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

IPC分类号： G06F12/08 ,  G11C29/02 ,  G11C29/10 ,  G11C29/50 ,  G06F12/00

CPC分类号： G11C29/50012 ,  G06F12/0831 ,  G11C29/02 ,  G11C29/50 ,  G06F2212/1032 ,  G11C15/00 ,  G11C29/10

摘要： A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred. If the snoop cycle occurred prior to completing the memory operation, the predetermined delay is increased and the test is repeated for the increased delay. Prior to repeating the test, the cache line's coherency with external memory is checked for conformance with the cache protocol. Additionally, the test unit may further be programmed to detect an occurrence of certain external local bus signals generated by the cache memory subsystem, such as a signal indicating a hit to a cache line occurred, and a signal indicating that a hit to a modified line in the cache occurred. The test is repeated until it is determined that the snoop cycle has not occurred upon completion of the line fill instruction.

摘要翻译： 高速缓存存储器子系统的测试方法包括设置测试单元以在经过预定延迟时在局部总线上发起窥探周期。 预定的延迟最初被设置为非常短的延迟或零延迟。 要执行的侦听周期可以以查询周期的形式到预定的存储器地址。 测试单元进一步设置或编程为开始监视局部总线的某些活动，包括指示是否发生窥探周期的活动。 在对测试单元进行编程之后，处理器核心执行与窥探周期的地址相关联的存储器操作。 该存储器操作导致高速缓存行转换。 在某一时刻，在存储器操作之前，期间或之后，通过测试单元根据预定的延迟执行窥探周期。 在完成存储器操作时，从测试单元读取状态寄存器以确定窥探周期是否仍然发生。 如果在完成存储器操作之前发生探听周期，则增加预定延迟并且为了延长延迟重复测试。 在重复测试之前，检查缓存行与外部存储器的一致性是否符合缓存协议。 此外，测试单元还可以被编程为检测由高速缓存存储器子系统产生的某些外部局部总线信号的发生，例如指示发生高速缓存线的命中的信号，以及指示对修改的线的命中的信号 在缓存中发生。 重复该测试，直到确定在行填充指令完成后探测周期未发生。