公开(公告)号：US06423590B2

公开(公告)日：2002-07-23

申请号：US09846538

申请日：2001-05-02

Applicant: Jun-Lin Tsai ,  Ruey-Hsin Lin ,  Jei-Feng Hwang ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsin Lin ,  Jei-Feng Hwang ,  Kuo-Chio Liu

IPC: H01L2100

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/7322

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract translation: 公开了一种用于高电压双极晶体管的新设计。 代替埋置的子集电极（在NPN器件中将为N +），使用掩埋的P +层。 该P +层的存在导致其本身和双极基底之间的夹断。 这样可以实现更高的击穿电压。 特别地，该装置不会在作为常规装置的弱点的基极 - 集电极结的底部分解。 对该装置的制造方法进行说明。 这个新工艺的一个特点是在P +层上生长的N型外延层只是传统器件中其对应厚度的大约一半。 该工艺与传统的BiCMOS工艺完全兼容，成本较低。