公开(公告)号：US20130002213A1

公开(公告)日：2013-01-03

申请号：US13170679

申请日：2011-06-28

Applicant: Rupesh Khare ,  Nitin Bansal

Inventor： Rupesh Khare ,  Nitin Bansal

IPC: G05F1/10

CPC classification number: G05F1/563

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Abstract translation: 调节器结构包括具有耦合到参考电压节点的第一输入的第一差分放大器。 第二差分放大器具有耦合到第一差分放大器的输出的第一输入。 第三差分放大器具有耦合到第一差分放大器的输出的第一输入。 第一pmos晶体管的栅极耦合到第二差分放大器输出，其漏极耦合到第一和第二差分放大器中的每一个的第二输入端。 第二pmos晶体管的栅极耦合到第三差分放大器输出，其漏极被配置为输出也是第三差分放大器的第二输入的调节电压。 电路被配置为复制经调节的电压并将复制的调节电压耦合到第一pmos晶体管的漏极。

公开(公告)号：US07602162B2

公开(公告)日：2009-10-13

申请号：US11604655

申请日：2006-11-27

Applicant: Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

Inventor： Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

IPC: G05F1/573

CPC classification number: G05F1/573

Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.

Abstract translation: 具有N型传输晶体管的线性稳压器包括过流保护电路。 电流吸收器用作过电流状态的指示器，并且耦合到线性稳压器的输出。 该指示器耦合到控制通过输出负载的电流的反馈逻辑电路。 过电流保护电路广泛地使用N型器件用于各种部件，包括电路中的输出驱动级。 这导致过流保护电路的面积减小。

公开(公告)号：US20070194768A1

公开(公告)日：2007-08-23

申请号：US11604655

申请日：2006-11-27

Applicant: Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

Inventor： Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

IPC: G05F1/573 ,  G05F3/16

CPC classification number: G05F1/573

Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.

Abstract translation: 具有N型传输晶体管的线性稳压器包括过流保护电路。 电流吸收器用作过电流状态的指示器，并且耦合到线性稳压器的输出。 该指示器耦合到控制通过输出负载的电流的反馈逻辑电路。 过电流保护电路广泛地使用N型器件用于各种部件，包括电路中的输出驱动级。 这导致过流保护电路的面积减小。

公开(公告)号：US08710809B2

公开(公告)日：2014-04-29

申请号：US13170679

申请日：2011-06-28

Applicant: Rupesh Khare ,  Nitin Bansal

Inventor： Rupesh Khare ,  Nitin Bansal

IPC: G05F1/00

CPC classification number: G05F1/563

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Abstract translation: 调节器结构包括具有耦合到参考电压节点的第一输入的第一差分放大器。 第二差分放大器具有耦合到第一差分放大器的输出的第一输入。 第三差分放大器具有耦合到第一差分放大器的输出的第一输入。 第一pmos晶体管的栅极耦合到第二差分放大器输出，其漏极耦合到第一和第二差分放大器中的每一个的第二输入端。 第二pmos晶体管的栅极耦合到第三差分放大器输出，其漏极被配置为输出也是第三差分放大器的第二输入的调节电压。 电路被配置为复制经调节的电压并将复制的调节电压耦合到第一pmos晶体管的漏极。