公开(公告)号：US20240160593A1

公开(公告)日：2024-05-16

申请号：US18056012

申请日：2022-11-16

Applicant: STMicroelectronics S.r..l.

Inventor： Marco Castellano ,  Francesco Bruni ,  Luca Gandolfi ,  Marco Leo

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  G06F2213/40

Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

公开(公告)号：US20190222938A1

公开(公告)日：2019-07-18

申请号：US16226146

申请日：2018-12-19

Applicant: STMicroelectronics S.r. l.

Inventor： Antonio Silverio

IPC: H04R5/04 ,  H04S3/00 ,  H04J3/06 ,  H03L7/18

CPC classification number: H04R5/04 ,  H03L7/18 ,  H04J3/0644 ,  H04J3/0652 ,  H04N21/41422 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/434 ,  H04N21/4392 ,  H04N21/8106 ,  H04S3/00 ,  H04S2400/01

Abstract: In accordance with an embodiment, a method of producing a TDM serial audio stream includes: receiving a plurality of input audio signal streams from an audio source clocked at an input clock frequency and producing therefrom a TDM serial output stream clocked at a TDM output clock frequency; obtaining the input clock frequency and the TDM output clock frequency by dividing a master clock frequency; writing audio signal samples from the input audio signal streams into a set of memory buffers at the input clock frequency; and producing the TDM serial output stream from audio signal samples buffered in the memory buffers by reading the buffered audio signal samples at the TDM output clock frequency.

公开(公告)号：US20240212714A1

公开(公告)日：2024-06-27

申请号：US18597484

申请日：2024-03-06

Applicant: STMicroelectronics KK ,  STMicroelectronics S.r. l.

Inventor： Marco Ferrari ,  Davide Betta ,  Diego Tognoli ,  Roberto Trabattoni

IPC: G11B21/08

CPC classification number: G11B21/083

Abstract: In accordance with an embodiment, a hard disk drive includes voice coil motors (VCMs) coupled to respective control units configured to drive retract an operation of the VCMs in the hard disk drive. The retract operation of the VCMs includes a sequence of retract steps. The control units are allotted respective time slots for communication over a communication line with the respective time slots synchronized via the common clock line, and are configured to drive sequences of retract steps of the VCMs in the hard disk drive in a timed relationship.

公开(公告)号：US20150381186A1

公开(公告)日：2015-12-31

申请号：US14741731

申请日：2015-06-17

Applicant: STMICROELECTRONICS S.r. l.

Inventor： Angelo SCUDERI ,  Antonino Calcagno ,  Salvatore Scaccianoce

IPC: H03L7/02 ,  H04B1/38

CPC classification number: H03L7/02 ,  H03B2202/06 ,  H03C1/62 ,  H03L7/18 ,  H04B1/0475 ,  H04B1/38 ,  H04B7/00 ,  H04L25/4902

Abstract: An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency.

Abstract translation: 振荡器电路可以包括本地振荡器以产生具有可调频率的载波信号，第一调制器和功率放大器级联耦合到本地振荡器以产生输出信号。 可以从具有第一频率的第一调制信号激活第一调制器，第一频率交替地限定第一调制器的接通和断开状态。 估计单元可以在时间窗口期间接收载波信号，并且在ON和OFF状态期间检测载波信号的估计频率变化。 补偿单元可以包括第二调制器，以产生与估计的频率变化成比例并且以第二调制频率调制的补偿信号。 第二调制频率可以与第一调制频率基本相同，并且补偿信号可以被添加到本地振荡器的偏置信号以调谐可调谐频率。