公开(公告)号：US06467070B2

公开(公告)日：2002-10-15

申请号：US09808344

申请日：2001-03-15

申请人： Sachi Kuroda ,  Toshiaki Sugioka ,  Toru Osajima ,  Shigenori Ichinose

发明人： Sachi Kuroda ,  Toshiaki Sugioka ,  Toru Osajima ,  Shigenori Ichinose

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.

摘要翻译： 一种用于半导体器件的设计支持装置，其用于在设计时快速地布置用于减少来自半导体器件的电磁辐射的非逻辑单元。 在这种用于半导体器件的设计支持装置中，布局部分对逻辑单元和布线图案进行布局以连接逻辑单元。 在布局部分进行布局之后，排列位置检测部分检测作为不包含逻辑单元或禁止区域的位置的排列位置。 非逻辑单元图形存储部分存储非逻辑单元图案。 含有现场检测部分的禁止区域检测禁止区域的包含场地，作为仅包含禁止区域的场所。 非逻辑单元布置部分在布置的位置上布置非逻辑单元。 此外，非逻辑单元布置部分将禁止区域的禁止区域的布置与非逻辑单元图案进行比较，并且将非逻辑单元仅在彼此不冲突的位置排列。