公开(公告)号：US07844934B2

公开(公告)日：2010-11-30

申请号：US11486107

申请日：2006-07-14

申请人： Yusaku Ono ,  Osamu Suga ,  Kazuyuki Sakata ,  Hirofumi Taguchi ,  Yushi Okuno ,  Toshiaki Sugioka ,  Daisuke Kondo

发明人： Yusaku Ono ,  Osamu Suga ,  Kazuyuki Sakata ,  Hirofumi Taguchi ,  Yushi Okuno ,  Toshiaki Sugioka ,  Daisuke Kondo

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072 ,  G06F17/5068

摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.

摘要翻译： 根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪层级单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

公开(公告)号：US20070124714A1

公开(公告)日：2007-05-31

申请号：US11486107

申请日：2006-07-14

申请人： Yusaku Ono ,  Osamu Suga ,  Kazuyuki Sakata ,  Hirofumi Taguchi ,  Yushi Okuno ,  Toshiaki Sugioka ,  Daisuke Kondo

发明人： Yusaku Ono ,  Osamu Suga ,  Kazuyuki Sakata ,  Hirofumi Taguchi ,  Yushi Okuno ,  Toshiaki Sugioka ,  Daisuke Kondo

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068

摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.

摘要翻译： 根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪分层单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

公开(公告)号：US06467070B2

公开(公告)日：2002-10-15

申请号：US09808344

申请日：2001-03-15

申请人： Sachi Kuroda ,  Toshiaki Sugioka ,  Toru Osajima ,  Shigenori Ichinose

发明人： Sachi Kuroda ,  Toshiaki Sugioka ,  Toru Osajima ,  Shigenori Ichinose

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.

摘要翻译： 一种用于半导体器件的设计支持装置，其用于在设计时快速地布置用于减少来自半导体器件的电磁辐射的非逻辑单元。 在这种用于半导体器件的设计支持装置中，布局部分对逻辑单元和布线图案进行布局以连接逻辑单元。 在布局部分进行布局之后，排列位置检测部分检测作为不包含逻辑单元或禁止区域的位置的排列位置。 非逻辑单元图形存储部分存储非逻辑单元图案。 含有现场检测部分的禁止区域检测禁止区域的包含场地，作为仅包含禁止区域的场所。 非逻辑单元布置部分在布置的位置上布置非逻辑单元。 此外，非逻辑单元布置部分将禁止区域的禁止区域的布置与非逻辑单元图案进行比较，并且将非逻辑单元仅在彼此不冲突的位置排列。

公开(公告)号：US07032198B2

公开(公告)日：2006-04-18

申请号：US10634815

申请日：2003-08-06

申请人： Masahiro Sano ,  Toshiaki Sugioka

发明人： Masahiro Sano ,  Toshiaki Sugioka

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method for designing an integrated circuit such as a VLSI circuit, in particular optimizing delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be decreased. The method can include determining whether the signal source satisfies a fan-out restriction if the signal source supplies a signal to all of the driven elements which are directly connected to the signal source, dividing the elements into groups so that the fan-out restriction is satisfied in each of the groups and each of the groups has the same or substantially same load capacity, when the signal source does not satisfy the fan-out restriction, and inserting into each group, a buffer having a size which makes the groups of elements satisfy the fan-out restriction. The dividing and the buffer inserting are repeated until a positive determination is delivered on the fan-out restriction.

摘要翻译： 一种用于设计诸如VLSI电路的集成电路的方法，特别是优化通过将信号提供源连接到每个元件的信号线的信号的延迟，由此可以减少偏斜。 该方法可以包括：如果信号源向直接连接到信号源的所有驱动元件提供信号，则确定信号源是否满足扇出限制，将这些元件分成组，使得扇出限制是 满足每个组，并且每个组中的每个组具有相同或基本上相同的负载能力，当信号源不满足扇出限制时，并且将每个组中插入具有使组成元素的大小的缓冲器 满足扇出限制。 重复分割和缓冲器插入，直到在扇出限制上传送肯定的确定。

公开(公告)号：US07051311B2

公开(公告)日：2006-05-23

申请号：US10445822

申请日：2003-05-28

申请人： Katsuko Tomita ,  Toshiaki Sugioka ,  Katsutoshi Baba

发明人： Katsuko Tomita ,  Toshiaki Sugioka ,  Katsutoshi Baba

IPC分类号： G06F17/50 ,  H01L29/00

CPC分类号： G06F17/5077 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor circuit designing method, comprising a lower level hierarchical designing step of designing a semiconductor circuit inside a block and an upper level hierarchical designing step of designing an external wiring of the block. The above-mentioned lower level hierarchical designing step or upper level hierarchical designing step includes a shield wiring designing step of designing to provide a shield wiring on a boundary part of the block.

公开(公告)号：US06651224B1

公开(公告)日：2003-11-18

申请号：US09600144

申请日：2000-07-12

申请人： Masahiro Sano ,  Toshiaki Sugioka

发明人： Masahiro Sano ,  Toshiaki Sugioka

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： There is provided a method utilized when designing an integrated circuit such as a VLSI or the like. The method is utilized for optimizing the delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be positively decreased. The method includes a step (S511) of determining whether or not the signal supplying source satisfies a fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source, a step (S514) of dividing the plurality of elements into a plural number of groups so that the fan-out restriction is satisfied in each of the groups and that each of the groups has the same or substantially the same load capacity, when it is determined that the signal supplying source does not satisfy the fan-out restriction, and a step (S515) of inserting into each of the groups, a buffer element having a size which makes the groups of elements satisfy the fan-out restriction. The buffer element inserted at the buffer inserting step (S515) is regarded as a driven element and then it is again determined in the determining step (S511) whether or not the signal supplying source satisfies the fan-out restriction under the condition that the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source. The dividing step (S514) and the buffer inserting step (S515) are repeatedly carried out until positive determination is delivered on the fan-out restriction.

摘要翻译： 提供了在设计诸如VLSI等的集成电路时使用的方法。 该方法用于优化通过将信号提供源连接到每个元件的信号线传输的信号的延迟，由此可以肯定地减少歪斜。 该方法包括步骤（S511），如果信号提供源向直接连接到信号提供源的所有驱动元件提供信号，则确定信号提供源是否满足扇出限制，步骤（ S514），将多个要素划分为多个组，使得在每个组中满足扇出限制，并且每个组具有相同或基本上相同的负载能力，当确定 信号供给源不满足扇出限制的步骤（S515），并且向每个组插入具有使该组元件满足扇出限制的尺寸的缓冲元件的步骤（S515）。 在缓冲器插入步骤（S515）中插入的缓冲元件被认为是从动元件，然后在确定步骤（S511）中再次确定信号提供源是否满足扇出限制，条件是信号 供应源向直接连接到信号提供源的所有驱动元件提供信号。 重复执行分割步骤（S514）和缓冲器插入步骤（S515），直到在扇出限制上传送肯定确定。