公开(公告)号：US20110161066A1

公开(公告)日：2011-06-30

申请号：US12648600

申请日：2009-12-29

Applicant: Sachin Kakkar ,  John Ries

Inventor： Sachin Kakkar ,  John Ries

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5022

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract translation: 本发明的方面旨在通过操纵系统模型中的延迟来减少三角周期执行来提高事件驱动模拟的速度。 以对设计者可能感兴趣的系统的选定信号上保留增量周期精确定时的方式执行操作。 提供了用于识别感兴趣的信号的方法和系统，并且用于确定可能使三角波延迟重新定时的设计部分。 保留感兴趣信号的时间安排，可以使设计人员仍然可以看到感兴趣的信号中的设计中出现的竞争条件和毛刺。 为了减少模拟时间，增量延迟可以从高活动信号移动到低活动信号，增量延迟的总数可以减少，或者可以减少执行的处理的数量。

公开(公告)号：US08346529B2

公开(公告)日：2013-01-01

申请号：US12648600

申请日：2009-12-29

Applicant: Sachin Kakkar ,  John Ries

Inventor： Sachin Kakkar ,  John Ries

IPC: G06F17/50 ,  G06F9/455 ,  G06G7/62 ,  G06G7/54

CPC classification number: G06F17/5009 ,  G06F17/5022

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract translation: 本发明的方面旨在通过操纵系统模型中的延迟来减少三角周期执行来提高事件驱动模拟的速度。 以对设计者可能感兴趣的系统的选定信号上保留增量周期精确定时的方式执行操作。 提供了用于识别感兴趣的信号的方法和系统，并且用于确定可能使三角波延迟重新定时的设计部分。 保留感兴趣信号的时间安排，可以使设计人员仍然可以看到感兴趣的信号中的设计中出现的竞争条件和毛刺。 为了减少模拟时间，增量延迟可以从高活动信号移动到低活动信号，增量延迟的总数可以减少，或者可以减少执行的处理的数量。

公开(公告)号：US20120011481A1

公开(公告)日：2012-01-12

申请号：US13167415

申请日：2011-06-23

Applicant: Pankaj Kumar Dwivedi ,  Amit Srivastava ,  Sachin Kakkar ,  Rudra Mukherjee

Inventor： Pankaj Kumar Dwivedi ,  Amit Srivastava ,  Sachin Kakkar ,  Rudra Mukherjee

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.

Abstract translation: 本发明提供了用于生成电子设计的功率行为的分层表示的技术和装置。 在一些实现中，从电子设计的功率规格中提取表示电子设计的功率特性的平坦有限状态机。 随后，从平坦有限状态机，功率规范和逻辑规范生成用于功率特性的分级有限状态机表示。

公开(公告)号：US08943451B2

公开(公告)日：2015-01-27

申请号：US13167415

申请日：2011-06-23

Applicant: Pankaj Kumar Dwivedi ,  Amit Srivastava ,  Sachin Kakkar ,  Rudra Mukherjee

Inventor： Pankaj Kumar Dwivedi ,  Amit Srivastava ,  Sachin Kakkar ,  Rudra Mukherjee

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.

Abstract translation: 本发明提供了用于生成电子设计的功率行为的分层表示的技术和装置。 在一些实现中，从电子设计的功率规格中提取表示电子设计的功率特性的平坦有限状态机。 随后，从平坦有限状态机，功率规范和逻辑规范生成用于功率特性的分级有限状态机表示。