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    Method for manufacturing a capacitor lower electrode over a transistor and a bit line corresponding to a cell area of a semiconductor device
    1.
    发明授权
    Method for manufacturing a capacitor lower electrode over a transistor and a bit line corresponding to a cell area of a semiconductor device 失效
    在晶体管上制造电容器下电极的方法和对应于半导体器件的单元区域的位线

    公开(公告)号：US06667208B2

    公开(公告)日：2003-12-23

    申请号：US10184575

    申请日：2002-06-28

    申请人： Sang-ryong Oh ,  Jung-guk Kim ,  Jin-ho Park ,  Ki-won Nam

    发明人： Sang-ryong Oh ,  Jung-guk Kim ,  Jin-ho Park ,  Ki-won Nam

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L21/32136 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

    摘要： Disclosed is method for manufacturing a semiconductor device, wherein a photosensitive layer and a natural oxidation layer on a cell area and a peripheral circuit area are removed by dry etching while a capacitor of a DRAM device is manufactured, and a polysilicon layer which is not used in the following process is removed by controlling the composition ratio of CF4 gas and O2 gas and the change of pressure and electrical power in two steps so as to reduce the etching selection ratio of the photosensitive layer and the natural oxidation layer with respect to the polysilicon, whereby the remaining polysilicon is prevented regardless of the etching time and etching amount.

    摘要翻译： 公开了制造半导体器件的方法，其中在制造DRAM器件的电容器的同时，通过干蚀刻除去电池区域和外围电路区域上的感光层和自然氧化层，以及未使用的多晶硅层 通过两步控制CF 4气体和O 2气体的组成比和压力和电功率的变化来除去以下过程，以便降低感光层和天然氧化层相对于多晶硅的蚀刻选择比 ，从而防止了剩余的多晶硅，而与蚀刻时间和蚀刻量无关。

    Method for setting plasma chamber having an adaptive plasma source, plasma etching method using the same and manufacturing method for adaptive plasma source
    2.
    发明申请
    Method for setting plasma chamber having an adaptive plasma source, plasma etching method using the same and manufacturing method for adaptive plasma source 审中-公开
    用于设置具有自适应等离子体源的等离子体室的方法，使用其的等离子体蚀刻方法和用于自适应等离子体源的制造方法

    公开(公告)号：US20070151947A1

    公开(公告)日：2007-07-05

    申请号：US10583976

    申请日：2004-12-22

    申请人： Yeong Song ,  Sang Ryong Oh ,  Sheung Kim ,  Nam Kim ,  Young Oh ,  Do Hyung Lee

    发明人： Yeong Song ,  Sang Ryong Oh ,  Sheung Kim ,  Nam Kim ,  Young Oh ,  Do Hyung Lee

    IPC分类号： C23F1/00 ,  H01L21/302 ,  C03C15/00

    CPC分类号： C23F4/00 ,  H01J37/321 ,  H01J37/32935 ,  H01J2237/334 ,  H01L21/32136 ,  H01L21/32137 ,  H05H1/46

    摘要： Disclosed herein is a plasma chamber setting method for generating plasma in a plasma chamber. A plurality of plasma source coils, including a first plasma source coil, a second plasma source coil having an etching rate at the center part thereof higher than that of the first plasma source coil, and a third plasma source coil having an etching rate at the edge part thereof higher than that of the first plasma source coil, are prepared. The first plasma source coil is disposed on the plasma chamber, and a test wafer is etched. The etching rate for each position of the test wafer is analyzed, and first plasma source coil is replaced with the second plasma source coil or the third plasma source coil based on the analysis results.

    摘要翻译： 这里公开了一种用于在等离子体室中产生等离子体的等离子体室设定方法。 多个等离子体源线圈，包括第一等离子体源线圈，其中心部分处的蚀刻速率高于第一等离子体源线圈的蚀刻速率的第二等离子体源线圈，以及在第 其边缘部分高于第一等离子体源线圈的边缘部分。 第一等离子体源线圈设置在等离子体室上，蚀刻测试晶片。 分析测试晶片的每个位置的蚀刻速率，并且基于分析结果，用第二等离子体源线圈或第三等离子体源线圈替换第一等离子体源线圈。