公开(公告)号：US20210103662A1

公开(公告)日：2021-04-08

申请号：US17127122

申请日：2020-12-18

申请人： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

发明人： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

IPC分类号： G06F21/57 ,  G06F8/65 ,  G06F21/44 ,  G06F21/10

摘要： Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

公开(公告)号：US06779065B2

公开(公告)日：2004-08-17

申请号：US09945419

申请日：2001-08-31

申请人： Keshav Murty ,  Scott Bobholz

发明人： Keshav Murty ,  Scott Bobholz

IPC分类号： G06F948

CPC分类号： G06F9/4812 ,  G06F9/4843

摘要： The present invention provides a mechanism for handling interrupts on a processor that supports multiple-threads concurrently. The processor's resources are allocated to provide multiple logical processors. In response to a common interrupt, the logical processors vie for access to a shared register. The first logical processor to access the shared register handles the common interrupt. The remaining logical processors return from the interrupt.

摘要翻译： 本发明提供了一种用于处理同时支持多线程的处理器上的中断的机制。 处理器的资源被分配以提供多个逻辑处理器。 响应于一个共同的中断，逻辑处理器可以访问共享寄存器。 访问共享寄存器的第一个逻辑处理器处理公共中断。 剩余的逻辑处理器从中断返回。