公开(公告)号：US20210103662A1

公开(公告)日：2021-04-08

申请号：US17127122

申请日：2020-12-18

申请人： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

发明人： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

IPC分类号： G06F21/57 ,  G06F8/65 ,  G06F21/44 ,  G06F21/10

摘要： Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

公开(公告)号：US11080045B2

公开(公告)日：2021-08-03

申请号：US13993483

申请日：2011-12-22

申请人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

发明人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US09960917B2

公开(公告)日：2018-05-01

申请号：US13995453

申请日：2011-12-22

申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC分类号： G06F9/30 ,  H04L9/28 ,  H04L9/06

CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30036 ,  H04L9/0643

摘要： A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.

公开(公告)号：US09772845B2

公开(公告)日：2017-09-26

申请号：US13976184

申请日：2011-12-13

申请人： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

发明人： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC分类号： G06F9/30 ,  H04L9/06

CPC分类号： G06F9/30145 ,  H04L9/0643 ,  H04L2209/122

摘要： A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

公开(公告)号：US09747105B2

公开(公告)日：2017-08-29

申请号：US12653704

申请日：2009-12-17

申请人： Vinodh Gopal ,  James D. Guilford ,  Erdine Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

发明人： Vinodh Gopal ,  James D. Guilford ,  Erdine Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F1/02 ,  G06F17/50 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

公开(公告)号：US09652234B2

公开(公告)日：2017-05-16

申请号：US13996352

申请日：2011-09-30

申请人： Paul Caprioli ,  Martin G. Dixon ,  Brett L. Toll ,  Muawya M. Al-Otoom ,  Omar M. Shaikh

发明人： Paul Caprioli ,  Martin G. Dixon ,  Brett L. Toll ,  Muawya M. Al-Otoom ,  Omar M. Shaikh

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3808 ,  G06F9/3877 ,  G06F9/3887

摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.

公开(公告)号：US20160239304A1

公开(公告)日：2016-08-18

申请号：US14757857

申请日：2015-12-26

申请人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

发明人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F9/46

CPC分类号： G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

摘要翻译： 本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。 硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件， 或其组合基于跟踪的中止事件进行中止判定。 作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。 在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。 并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

公开(公告)号：US09405537B2

公开(公告)日：2016-08-02

申请号：US13997186

申请日：2011-12-22

申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC分类号： G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC分类号： G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

摘要翻译： 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US09100184B2

公开(公告)日：2015-08-04

申请号：US13976741

申请日：2011-12-22

申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC分类号： H04L29/00 ,  H04L9/28 ,  H04L9/06 ,  G06F21/72

CPC分类号： H04L9/28 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/122

摘要： A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.

摘要翻译： 一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。 该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。 该指令还指示具有表示消息和常数数据的数据元素的第二源。 响应该指令，结果存储在指令指示的目的地中。 结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。 四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

公开(公告)号：US20150199198A1

公开(公告)日：2015-07-16

申请号：US13997857

申请日：2011-12-29

申请人： Adriaan Van De Ven ,  Baiju V. Patel ,  Asit K. Mallick ,  Gilbert Neiger ,  James S. Coke ,  Martin G. Dixon ,  Jason W. Brandt

发明人： Adriaan Van De Ven ,  Baiju V. Patel ,  Asit K. Mallick ,  Gilbert Neiger ,  James S. Coke ,  Martin G. Dixon ,  Jason W. Brandt

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30043 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1491

摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.

摘要翻译： 公开了用于监督模式执行保护的装置和方法。 在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。 存储器中的区域是用户存储器。 执行硬件是执行指令。 当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。