公开(公告)号：US20130322417A1

公开(公告)日：2013-12-05

申请号：US13904002

申请日：2013-05-28

申请人： Sean Kao

发明人： Sean Kao

IPC分类号： H04W88/06

CPC分类号： H04W88/06 ,  H04B2201/70714 ,  H04L23/02 ,  H04L27/0008 ,  H04L27/2601 ,  H04W80/02 ,  H04W84/12

摘要： A method of transceiving data includes providing a wireless transceiver chip that supports multiple wireless standards for transceiving data packets, wherein a first wireless standard comprises a first modulation and demodulation scheme, and wherein a second wireless standard comprises a second modulation and demodulation scheme, and wherein the first modulation and demodulation scheme is incompatible with the second modulation and demodulation scheme; activating only one PHY layer of the wireless transceiver chip during the transceiving of the data packets; using a MAC layer of the wireless transceiver chip to specify whether the first or second wireless standard is to be used for a given transceiving of the data packets; and the PHY layer receiving instructions from the MAC layer regarding which wireless standard is to be used for the transceiving of the data packets using hardware that is shared by the PHY layer corresponding to both wireless standards.

摘要翻译： 一种收发数据的方法包括提供一种无线收发器芯片，其支持用于收发数据分组的多个无线标准，其中第一无线标准包括第一调制和解调方案，并且其中第二无线标准包括第二调制和解调方案，并且其中 第一调制解调方案与第二调制解调方案不兼容; 在收发数据包期间只激活无线收发器芯片的一个PHY层; 使用无线收发器芯片的MAC层来指定是否将第一或第二无线标准用于给定的数据包的收发; 并且PHY层从MAC层接收关于哪个无线标准将用于使用与两个无线标准对应的PHY层共享的硬件来收发数据分组的指令。

公开(公告)号：US07477072B1

公开(公告)日：2009-01-13

申请号：US11333972

申请日：2006-01-17

申请人： Sean Kao ,  Arifur Rahman ,  James Anderson

发明人： Sean Kao ,  Arifur Rahman ,  James Anderson

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

摘要： A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a configurable logic block; and a reset signal coupled to the block of memory elements, the reset signal enabling partial reconfiguration of the memory cells of the configurable logic block. Each the memory cell may be coupled to receive the reset signal enabling the partial reconfiguration of the block of memory cells of the configurable logic block. The reset signal may comprise a plurality of signals, wherein each signal of the plurality of signals is coupled to a memory cell of the block of memory cells. Each memory cell may also receive a signal for setting an initial state. A method of enabling partial reconfiguration of memory cells of a look-up table of a programmable logic device is also described.

摘要翻译： 描述了一种用于实现具有可编程逻辑的设备的存储器元件的部分重新配置的电路。 该电路包括一组存储器单元，其包括可配置逻辑块的查找表; 以及耦合到所述存储器单元块的复位信号，所述复位信号使得能够对所述可配置逻辑块的存储器单元进行部分重新配置。 每个存储器单元可以被耦合以接收复位信号，从而能够对可配置逻辑块的存储器单元块进行部分重新配置。 复位信号可以包括多个信号，其中多个信号中的每个信号耦合到存储器单元块的存储单元。 每个存储单元也可以接收用于设置初始状态的信号。 还描述了启用可编程逻辑器件的查找表的存储器单元的部分重新配置的方法。