公开(公告)号：US06356997B1

公开(公告)日：2002-03-12

申请号：US09679131

申请日：2000-10-04

申请人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

发明人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

IPC分类号： G06F9455

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3885

摘要： A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instruction includes a separate branch instruction and a branch control instruction, while in the second instruction set, a second type branch instruction includes only a branch instruction. The processor is optimized to handle the first instruction set so that the branch instruction is arrangeable in a program sequence so that an execution unit in the processor can compute a branch target address based on the branch control instruction without a latency penalty. The first type branch instructions also include a folded-compare format, while the second type branch instructions have separated compare and branch instructions. To handle the second type branch instructions, they may be converted into first type branch instructions so they can be executed in emulated form by the processor.

摘要翻译： 公开了一种双模式分支和分支控制系统和方法，用于容纳可以以两种操作模式中的任一种操作的处理器，每种操作模式使用不同类型的分支指令。 在第一指令集中，第一类型分支指令包括单独的分支指令和分支控制指令，而在第二指令集中，第二类型分支指令仅包括分支指令。 处理器被优化以处理第一指令集，使得分支指令可以在程序序列中排列，使得处理器中的执行单元可以基于分支控制指令计算分支目标地址而没有延迟代价。 第一类型分支指令还包括折叠比较格式，而第二类型分支指令具有分离的比较和分支指令。 为了处理第二类分支指令，它们可以被转换成第一类型的分支指令，使得它们可以由处理器以仿真形式执行。

公开(公告)号：US06324643B1

公开(公告)日：2001-11-27

申请号：US09679471

申请日：2000-10-04

申请人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

发明人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

IPC分类号： G06F938

CPC分类号： G06F9/3885 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3846

摘要： A two level branch prediction system and method is disclosed for controlling instruction flow in a pipelined processor. A first prediction indicator associated with a branch instruction specifies whether a particular branch condition is likely to be satisfied. A second prediction indicator associated with a branch control instruction specifies whether a particular branch target instruction is likely to be needed by one or more of the branch instructions. The first prediction indicator is used to load branch target instructions as they are needed in response to decoding a branch instruction, while the second prediction indicator is used by prefetching logic within the processor to determine whether a particular branch target instruction should be speculatively loaded even before the associated branch instruction is executed. The first and second prediction indicators can be set in advance as bit fields in the branch and branch control instructions respectively so that the processor microarchitecture behavior can be set up and controlled in software to reduce branch latencies for a particular program. The second prediction indicators can be ranked as well so that the prefetching logic can prioritize speculative loadings in accordance with a desired strategy.

摘要翻译： 公开了一种用于控制流水线处理器中的指令流的两级分支预测系统和方法。 与分支指令相关联的第一预测指标指定特定分支条件是否可能被满足。 与分支控制指令相关联的第二预测指示器指定一个或多个分支指令是否可能需要特定分支目标指令。 第一预测指示符用于响应于对分支指令的解码而需要加载分支目标指令，而第二预测指标由处理器内的预取逻辑使用，以确定是否应该在特定的分支目标指令之前被推测加载 执行关联的分支指令。 第一和第二预测指标可以分别设置在分支和分支控制指令中的位字段，使得处理器微架构行为可以在软件中建立和控制以减少特定程序的分支延迟。 也可以对第二预测指标进行排序，使得预取逻辑可根据期望的策略对推测负荷进行优先级排序。

公开(公告)号：US06477639B1

公开(公告)日：2002-11-05

申请号：US09679593

申请日：2000-10-04

申请人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

发明人： Sivaram Krishnan ,  Sebastian Haviuj Ziesler

IPC分类号： G06F938

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3885

摘要： An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or more associated branch instructions. The branch control instruction also includes its own branch instruction prediction bit for specifying to a prefetcher within the processor whether a common branch instruction is likely to be needed by the processor, as well as a ranking field for specifying a preloading priority for the particular common branch instruction. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc. A separate prediction bit within the branch instruction specifies whether the branch is likely to be taken or not taken to a branch control unit in the processor, and it is these separate prediction bits that are considered by a branch control instruction for a group of branch instructions to determine the branch instruction prediction bit.

摘要翻译： 提供改进的分支指令和相关联的分支控制指令，用于优化处理流水线处理器内的分支操作的处理。 分支控制指令被调整为使得它可以在编程序列中的分支指令之前，并且提供分支目标地址计算信息，使得可以在执行一个或多个相关联的分支指令之前计算分支目标地址。 分支控制指令还包括其自身的分支指令预测位，用于向处理器内的预取器指定公共分支指令是否可能由处理器需要，以及用于指定特定公共分支的预加载优先级的等级字段 指令。 由于分支目标地址计算信息与实际分支指令分离，因此在分支指令本身内有更多的空间可用于允许其他新类型的操作，比如折叠比较，寄存器进行寄存器比较（包括与零值寄存器的比较 ），谓词评估等。分支指令中的单独的预测位指定分支是否可能被带到处理器中的分支控制单元，并且是分支控制所考虑的这些单独的预测比特 一组分支指令的指令来确定分支指令预测位。