摘要:
An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or mote associated branch instructions. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc.