Pipelined processor executing logical or mathematical operation specifying compare folded branch instruction
    1.
    发明授权
    Pipelined processor executing logical or mathematical operation specifying compare folded branch instruction 失效
    执行逻辑或数学运算的流水线处理器指定比较折叠分支指令

    公开(公告)号:US06772323B2

    公开(公告)日:2004-08-03

    申请号:US10288343

    申请日:2002-11-04

    IPC分类号: G06F938

    摘要: An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or mote associated branch instructions. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc.

    摘要翻译: 提供改进的分支指令和相关联的分支控制指令,用于优化处理流水线处理器内的分支操作的处理。 分支控制指令被调整为使得其可以在编程序列中的分支指令之前,并且提供分支目标地址计算信息,使得可以在执行一个或微微相关联的分支指令之前计算分支目标地址。 由于分支目标地址计算信息与实际分支指令分离,因此在分支指令本身内有更多的空间可用于允许其他新类型的操作,比如折叠比较,寄存器进行寄存器比较(包括与零值寄存器的比较 ),谓词评估等