公开(公告)号：US6167465A

公开(公告)日：2000-12-26

申请号：US82312

申请日：1998-05-20

申请人： Shaham Parvin ,  Gary M. Catlin

发明人： Shaham Parvin ,  Gary M. Catlin

IPC分类号： G06F13/28 ,  G06F13/14

CPC分类号： G06F13/28

摘要： Accordingly, the present invention provides a method and an apparatus of establishing multiple direct memory access connections between a peripheral and a main memory of a computer system. Each of the multiple direct memory access connection is managed in an improved manner such that one or more of the multiple direct memory access connections are non-real-time connections, but real-time operations may be performed on the data carried by the non-real time connections. In another aspect of the present invention, a driver may be implemented on the computer system to facilitate the establishment and maintenance of the multiple direct memory access connections. The present inventions reduce arbitration and system interrupt latencies and reduces the management burden of the direct memory access connections on a central processing unit of the computer system.

摘要翻译： 因此，本发明提供一种在计算机系统的外围设备和主存储器之间建立多个直接存储器访问连接的方法和装置。 多个直接存储器访问连接中的每一个以改进的方式进行管理，使得多个直接存储器访问连接中的一个或多个是非实时连接，但是可以对非实时连接携带的数据执行实时操作， 实时连接。 在本发明的另一方面，可以在计算机系统上实现驱动程序，以便于建立和维护多个直接存储器访问连接。 本发明减少仲裁和系统中断延迟并且减少计算机系统的中央处理单元上的直接存储器访问连接的管理负担。

公开(公告)号：US20090201923A1

公开(公告)日：2009-08-13

申请号：US12368064

申请日：2009-02-09

申请人： RAGHAVAN MENON ,  ADAM GOLDSTEIN ,  MARK D. GRISWOLD ,  MITRI I. HALABI ,  MOHAMMAD K. ISSA ,  AMIR LEHAVOT ,  SHAHAM PARVIN ,  XIAOYANG ZHENG

发明人： RAGHAVAN MENON ,  ADAM GOLDSTEIN ,  MARK D. GRISWOLD ,  MITRI I. HALABI ,  MOHAMMAD K. ISSA ,  AMIR LEHAVOT ,  SHAHAM PARVIN ,  XIAOYANG ZHENG

IPC分类号： H04L12/28

CPC分类号： H04L12/40058 ,  H04L12/6418

摘要： Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

摘要翻译： 本发明的实施例涉及具有单个逻辑级和至少一个物理级的交换结构的部分。 此外，交换结构的数据路径和控制路径可以去耦合，从而允许执行额外的处理，否则与匹配高数据速率的控制速率的情况相反。 换句话说，在高速链路上接收的数据信元可以分散在许多低速链路上; 因此，数据单元可以以高速度传送交换结构，同时可以以较低的速度处理与数据相关联的控制信息。 由于可以以较低的速度（与控制路径相关联）来处理控制信息，所以可以在更长的时间段内处理控制信息。

公开(公告)号：US07505458B2

公开(公告)日：2009-03-17

申请号：US09994592

申请日：2001-11-27

申请人： Raghavan Menon ,  Adam Goldstein ,  Mark D Griswold ,  Mitri I Halabi ,  Mohammad K Issa ,  Amir Lehavot ,  Shaham Parvin ,  Xiaoyang Zheng

发明人： Raghavan Menon ,  Adam Goldstein ,  Mark D Griswold ,  Mitri I Halabi ,  Mohammad K Issa ,  Amir Lehavot ,  Shaham Parvin ,  Xiaoyang Zheng

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L12/40058 ,  H04L12/6418

摘要： Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

摘要翻译： 本发明的实施例涉及具有单个逻辑级和至少一个物理级的交换结构的部分。 此外，交换结构的数据路径和控制路径可以去耦合，从而允许执行额外的处理，否则与匹配高数据速率的控制速率的情况相反。 换句话说，在高速链路上接收的数据信元可以分散在许多低速链路上; 因此，数据单元可以以高速度传送交换结构，同时可以以较低的速度处理与数据相关联的控制信息。 由于可以以较低的速度（与控制路径相关联）来处理控制信息，所以可以在更长的时间段内处理控制信息。

公开(公告)号：US08165112B2

公开(公告)日：2012-04-24

申请号：US12368064

申请日：2009-02-09

申请人： Raghavan Menon ,  Adam Goldstein ,  Mark D. Griswold ,  Mitri I. Halabi ,  Mohammad K. Issa ,  Amir Lehavot ,  Shaham Parvin ,  Xiaoyang Zheng

发明人： Raghavan Menon ,  Adam Goldstein ,  Mark D. Griswold ,  Mitri I. Halabi ,  Mohammad K. Issa ,  Amir Lehavot ,  Shaham Parvin ,  Xiaoyang Zheng

IPC分类号： H04L12/50

CPC分类号： H04L12/40058 ,  H04L12/6418

摘要： Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

摘要翻译： 本发明的实施例涉及具有单个逻辑级和至少一个物理级的交换结构的部分。 此外，交换结构的数据路径和控制路径可以去耦合，从而允许执行额外的处理，否则与匹配高数据速率的控制速率的情况相反。 换句话说，在高速链路上接收的数据信元可以分散在许多低速链路上; 因此，数据单元可以以高速度传送交换结构，同时可以以较低的速度处理与数据相关联的控制信息。 由于可以以较低的速度（与控制路径相关联）来处理控制信息，所以可以在更长的时间段内处理控制信息。

公开(公告)号：US06434645B1

公开(公告)日：2002-08-13

申请号：US09679322

申请日：2000-10-03

申请人： Shaham Parvin ,  Gary M. Catlin

发明人： Shaham Parvin ,  Gary M. Catlin

IPC分类号： G06F1314

CPC分类号： G06F13/28

摘要： Accordingly, the present invention provides a method and an apparatus of establishing multiple direct memory access connections between a peripheral and a main memory of a computer system. Each of the multiple direct memory access connection is managed in an improved manner such that one or more of the multiple direct memory access connections are non-real-time connections, but real-time operations may be performed the data carried by the non-real time connections. In another aspect of the present invention, a driver may be implemented on the computer system to facilitate the establishment and maintenance of the multiple direct memory access connections. The present inventions reduce arbitration and system interrupt latencies and reduces the management burden of the direct memory access connections on a central processing unit of the computer system.

摘要翻译： 因此，本发明提供一种在计算机系统的外围设备和主存储器之间建立多个直接存储器访问连接的方法和装置。 多个直接存储器访问连接中的每一个以改进的方式进行管理，使得多个直接存储器访问连接中的一个或多个是非实时连接，但是可以执行实时操作由非真实的 时间连接。 在本发明的另一方面，可以在计算机系统上实现驱动程序，以便于建立和维护多个直接存储器访问连接。 本发明减少仲裁和系统中断延迟并且减少计算机系统的中央处理单元上的直接存储器访问连接的管理负担。