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    Enhanced system, method and medium for certifying and accrediting requirements compliance utilizing continuous risk assessment
    1.
    发明授权
    Enhanced system, method and medium for certifying and accrediting requirements compliance utilizing continuous risk assessment 有权
    增强的系统，方法和媒介，用于通过持续风险评估来认证和认证需求合规性

    公开(公告)号：US06980927B2

    公开(公告)日：2005-12-27

    申请号：US10304826

    申请日：2002-11-27

    申请人： Richard P. Tracy ,  Hugh Barrett ,  Gary M. Catlin

    发明人： Richard P. Tracy ,  Hugh Barrett ,  Gary M. Catlin

    IPC分类号： G06F20060101 ,  G06F1/00 ,  G06F15/00 ,  G06F21/00 ,  G06Q10/10 ,  H04L29/06 ,  G06F17/60

    CPC分类号： H04L63/1433 ,  G06F21/577 ,  G06Q10/10 ,  H04L63/0823

    摘要： A computer-assisted system, medium and method of providing a risk assessment of a target system. The method includes electronically scanning, on a predetermined basis, hardware and/or software characteristics of components within a target system to obtain and store target system configuration information, receiving and storing target system operational environment information, using information collected in the scanning and receiving steps to select one or more security requirements in accordance with the at least one predefined standard, regulation and/or requirement, selecting one or more test procedures used to determine target system compliance with the security requirements, and producing a risk assessment of the target system.

    摘要翻译： 一种计算机辅助系统，介质和提供目标系统风险评估的方法。 该方法包括以预定的方式电子扫描目标系统内的组件的硬件和/或软件特性，以使用在扫描和接收步骤中收集的信息来获取和存储目标系统配置信息，接收和存储目标系统操作环境信息 根据至少一个预定义的标准，规定和/或要求来选择一个或多个安全要求，选择一个或多个用于确定目标系统符合安全要求的测试程序，以及产生目标系统的风险评估。

    Multiple processor accelerator for logic simulation
    2.
    发明授权
    Multiple processor accelerator for logic simulation 失效
    用于逻辑仿真的多处理器加速器

    公开(公告)号：US4873656A

    公开(公告)日：1989-10-10

    申请号：US67633

    申请日：1987-06-26

    申请人： Gary M. Catlin

    发明人： Gary M. Catlin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are also capable of operating independently of each other and communicate with each other and the host unit by a unidirectional token ring bus. A specialized hardwired processor design is implemented to provide a pipelined flow of data to provide a more rapid algotithm simulation.

    摘要翻译： 用于实现利用主处理器和布​​置在模块中的多个处理器的事件驱动算法的计算机，其中模块内的处理器能够彼此独立地操作。 各个模块还能够彼此独立地操作，并且通过单向令牌环总线彼此和主机单元进行通信。 实现专门的硬连线处理器设计来提供流水线数据流，以提供更快速的算法模拟。

    System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection
    3.
    发明授权
    System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection 失效
    用于管理外围设备和存储器之间的多个DMA连接并对由所选DMA连接承载的数据执行实时操作的系统

    公开(公告)号：US6167465A

    公开(公告)日：2000-12-26

    申请号：US82312

    申请日：1998-05-20

    申请人： Shaham Parvin ,  Gary M. Catlin

    发明人： Shaham Parvin ,  Gary M. Catlin

    IPC分类号： G06F13/28 ,  G06F13/14

    CPC分类号： G06F13/28

    摘要： Accordingly, the present invention provides a method and an apparatus of establishing multiple direct memory access connections between a peripheral and a main memory of a computer system. Each of the multiple direct memory access connection is managed in an improved manner such that one or more of the multiple direct memory access connections are non-real-time connections, but real-time operations may be performed on the data carried by the non-real time connections. In another aspect of the present invention, a driver may be implemented on the computer system to facilitate the establishment and maintenance of the multiple direct memory access connections. The present inventions reduce arbitration and system interrupt latencies and reduces the management burden of the direct memory access connections on a central processing unit of the computer system.

    摘要翻译： 因此，本发明提供一种在计算机系统的外围设备和主存储器之间建立多个直接存储器访问连接的方法和装置。 多个直接存储器访问连接中的每一个以改进的方式进行管理，使得多个直接存储器访问连接中的一个或多个是非实时连接，但是可以对非实时连接携带的数据执行实时操作， 实时连接。 在本发明的另一方面，可以在计算机系统上实现驱动程序，以便于建立和维护多个直接存储器访问连接。 本发明减少仲裁和系统中断延迟并且减少计算机系统的中央处理单元上的直接存储器访问连接的管理负担。

    Digital computer for implementing event driven simulation algorithm
    4.
    发明授权
    Digital computer for implementing event driven simulation algorithm 失效
    用于实现事件驱动仿真算法的数字计算机

    公开(公告)号：US4814983A

    公开(公告)日：1989-03-21

    申请号：US118295

    申请日：1987-11-06

    申请人： Gary M. Catlin

    发明人： Gary M. Catlin

    IPC分类号： G06F13/40 ,  G06F17/50 ,  G06F15/16

    CPC分类号： G06F17/5022 ,  G06F13/4027

    摘要： A computer for implementing an event driven algorithm which is used in conjunction with a master computer is disclosed. The computer includes a plurality of processors coupled in a ring arrangement each of which is microprogrammable. Each processor includes a memory and a memory address generator. The generator can generate addresses based on a combination of signals from both the microcode and signals on the data bus.

    摘要翻译： 公开了一种用于实现与主计算机结合使用的事件驱动算法的计算机。 计算机包括以环形布置耦合的多个处理器，每个处理器可微程序化。 每个处理器包括存储器和存储器地址发生器。 发生器可以基于来自数据总线上的微代码和信号的信号的组合来生成地址。

    Two-speed clock scheme for co-processors
    7.
    发明授权
    Two-speed clock scheme for co-processors 失效
    协同处理器的双速时钟方案

    公开(公告)号：US4677433A

    公开(公告)日：1987-06-30

    申请号：US851938

    申请日：1986-04-14

    申请人： Gary M. Catlin ,  Jim Klovstad

    发明人： Gary M. Catlin ,  Jim Klovstad

    IPC分类号： G06F9/38 ,  H04Q1/00

    CPC分类号： G06F9/3877 ,  G06F9/3869

    摘要： The present invention relates to a method and apparatus for a system utilizing a microprocessor having a faster maximum operating frequency and a numeric data processor having a slower maximum operating frequency which runs the system at the lower clocking frequency only during those times when both the microprocessor and the numeric data processor are required to perform processing functions and runs the system at the higher clocking frequency when only the microprocessor is required. Therefore the method and apparatus of the invention provides greater operating efficiency for the microprocessor, while not sacrificing the interface capabilities of the numeric data processor. In the apparatus of the present invention, the clocking frequencies are generated by a clocking generator which is coupled to both the microprocessor and the numeric data processor. The generator responds to signals from a control source to provide either the faster or the slower clocking frequency. The control source is responsive to program command such that it produces a first signal when the program does not require a numeric data processor to preform its processing functions and produces a second signal when the program requires te numeric data processor to perform its functions. In addition, a second signal from the source operates the reset of te numeric data processor.

    摘要翻译： 本发明涉及一种使用具有更快的最大工作频率的微处理器的系统的方法和装置，以及具有较慢的最大工作频率的数字数据处理器，该系统在较低的时钟频率下运行，仅在微处理器和 需要数字数据处理器来执行处理功能，并且仅在需要微处理器时以更高的时钟频率运行系统。 因此，本发明的方法和装置为微处理器提供更大的操作效率，同时不牺牲数字数据处理器的接口能力。 在本发明的装置中，时钟频率由耦合到微处理器和数字数据处理器的时钟发生器产生。 发生器响应来自控制源的信号，以提供更快或更慢的时钟频率。 控制源响应于程序命令，使得当程序不需要数字数据处理器来预处理其处理功能时产生第一信号，并且当程序要求数字数据处理器执行其功能时产生第二信号。 此外，来自源的第二信号操作数字数据处理器的复位。

    Programmable bus
    8.
    发明授权
    Programmable bus 失效
    可编程总线

    公开(公告)号：US06526518B1

    公开(公告)日：2003-02-25

    申请号：US09082650

    申请日：1998-05-20

    申请人： Gary M. Catlin ,  Edwin E. Everman, II

    发明人： Gary M. Catlin ,  Edwin E. Everman, II

    IPC分类号： G06F104

    CPC分类号： G06F13/362

    摘要： The present inventions provide apparatuses and methods for implementing a programmable bus. A programmable bus provides greater functionality and versatility through the ability to manage data transfers according to a number of sample rate clocks. The number of processing components connected to the programmable bus may be varied without a significant amount of physical alternations. Also, the number of data transfers for a given number of processing components may be modified and scheduled accordingly by reprogramming the programmable bus. The programmable bus comprises a bus and a bus arbiter. The bus is coupled to the bus arbiter and a plurality of devices and the bus arbiter. The plurality of devices operate at different sample rate clocks. The bus arbiter schedules and conducts the transfer of data between the plurality of devices according to the sample rate clocks such that the plurality of devices send and receive data at appropriate times, corresponding to the sample rate clocks. Thus, the bus arbiter is programmable due to the ability to configure the bus arbiter to schedule and conduct the transfer of data between and among the plurality of devices. The plurality of buses may include interface circuitry to allow them to interface properly with the programmable bus. Each device includes an input buffer and an output buffer, the input buffer having a first and a second buffer, and the output buffer having a first and a second buffer. The programmable bus is further comprised of a buffer select line carrying a buffer select signal, such that the buffer select signal informs the plurality of devices whether to use the first or the second buffer of the input and output buffers for the transfer of data. Double buffering facilitates, in one embodiment, the transfer of data based upon different sample rate clocks.

    摘要翻译： 本发明提供了用于实现可编程总线的装置和方法。 可编程总线通过根据多个采样率时钟管理数据传输的能力，提供更大的功能和多功能性。 连接到可编程总线的处理部件的数量可以不改变大量的物理变化而变化。 此外，可以通过重新编程可编程总线来相应地修改和调度给定数量的处理组件的数据传输的数量。 可编程总线包括总线和总线仲裁器。 总线耦合到总线仲裁器和多个设备和总线仲裁器。 多个设备以不同的采样率时钟操作。 总线仲裁器根据采样率时钟调度并进行多个设备之间的数据传输，使得多个设备在适当的时间对应于采样率时钟发送和接收数据。 因此，总线仲裁器是可编程的，因为能够配置总线仲裁器来调度和执行多个设备之间和之间的数据传输。 多个总线可以包括接口电路，以允许它们与可编程总线正确连接。 每个设备包括输入缓冲器和输出缓冲器，输入缓冲器具有第一和第二缓冲器，并且输出缓冲器具有第一和第二缓冲器。 可编程总线还包括一个载有缓冲选择信号的缓冲器选择线，使得缓冲器选择信号通知多个装置是否使用输入和输出缓冲器的第一或第二缓冲器来传送数据。 在一个实施例中，双缓冲有利于基于不同采样率时钟的数据传输。

    Multiple processor accelerator for logic simulation
    9.
    发明授权
    Multiple processor accelerator for logic simulation 失效
    用于逻辑仿真的多处理器加速器

    公开(公告)号：US4872125A

    公开(公告)日：1989-10-03

    申请号：US142721

    申请日：1988-01-11

    申请人： Gary M. Catlin

    发明人： Gary M. Catlin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are also capable of operating independently of each other and communicate with each other and the host unit by a unidirectional token ring bus. A specialized hardwired processor design is implemented to provide a pipelined flow of data to provide a more rapid simulation algorithm.

    摘要翻译： 用于实现利用主处理器和布​​置在模块中的多个处理器的事件驱动算法的计算机，其中模块内的处理器能够彼此独立地操作。 各个模块还能够彼此独立地操作，并且通过单向令牌环总线彼此和主机单元进行通信。 实现专门的硬连线处理器设计来提供流水线数据流，以提供更快速的模拟算法。