公开(公告)号：US20130182519A1

公开(公告)日：2013-07-18

申请号：US13352411

申请日：2012-01-18

申请人： Shi-Wen CHEN ,  Tsan-Tang Chen ,  Chi-Chang Shuai

发明人： Shi-Wen CHEN ,  Tsan-Tang Chen ,  Chi-Chang Shuai

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/14

摘要： A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.

摘要翻译： 存储器件包括存储单元阵列，第一和第二预充电开关电路，选择电路，辅助存储单元阵列，动态电压控制器和读出放大器。 辅助存储单元阵列包括辅助读位线和布置在列中并电连接到辅助读位线的多个存储单元。 第二预充电开关电路根据预充电控制信号来确定是否向每个上述存储单元提供参考电压。 动态电压控制器根据选择电路的输出信号的电压决定是否向辅助读取位线提供电压。 读出放大器将选择电路的输出信号的电压电平和辅助读取位线上的电压进行比较，从而相应地输出感测结果。

公开(公告)号：US20160289978A1

公开(公告)日：2016-10-06

申请号：US14678825

申请日：2015-04-03

申请人： Shi Wen CHEN

发明人： Shi Wen CHEN

IPC分类号： E04F13/08 ,  E04F13/076

CPC分类号： E04F13/0871 ,  E04F13/10 ,  E04F2203/02 ,  E04F2203/065

摘要： Present invention teaches the construction of a modular wood panels wherein a back plate, formed by two parallel strips and some rectangular pieces fitted between the two strips, serves to allow a decorative layer to be easily attached, with top-bottom and left-right interlocking mechanism; the use of the back plate materials allows low cost materials because a lot of scrap materials can be used, while contributing to better climate stability, in addition to ease of installation.

摘要翻译： 本发明教导了模块化木板的构造，其中由两个平行条形成的背板和装配在两个条之间的一些矩形片用于允许装饰层容易地附接，顶部和左右互锁 机制; 使用背板材料允许低成本材料，因为除了易于安装之外，可以使用大量废料，同时有助于更好的气候稳定性。

公开(公告)号：US20140035550A1

公开(公告)日：2014-02-06

申请号：US13565799

申请日：2012-08-03

申请人： Shi-Wen CHEN

发明人： Shi-Wen CHEN

IPC分类号： G05F3/02

CPC分类号： G05F3/08

摘要： A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage.

摘要翻译： 电压调节器电路包括多个晶体管和控制电路。 每个晶体管都有两个源极/漏极端子和一个栅极端子。 每个晶体管的一个源极/漏极端子电耦合到源极电压，并且晶体管的另一个源极/漏极端子彼此电耦合并且统称为电压调节器电路的输出端子。 控制电路电耦合到晶体管的栅极端子，并且被配置为根据输出端子处的电压与预定参考电压之间的差来确定要导通的晶体管的数量。

公开(公告)号：US20140023113A1

公开(公告)日：2014-01-23

申请号：US13555190

申请日：2012-07-23

申请人： Shi-Wen Chen

发明人： Shi-Wen Chen

IPC分类号： G01K7/01

CPC分类号： G01K7/01 ,  H03K3/0315

摘要： A temperature sensor includes a signal delaying apparatus, a comparison apparatus, a multiplier and a counting apparatus. The signal delaying apparatus is configured to receive a step signal, perform a phase delay operation on the received step signal according to a temperature degree, and thereby forming a first output signal. The comparison apparatus is configured to receive the first output signal and the step signal, and accordingly output a second output signal. The multiplier is configured to receive the second output signal and a clock signal, and accordingly output a third output signal. The counting apparatus is configured to receive the third output signal, count the number of pulses of the third output signal, and generate a digital code accordingly.

摘要翻译： 温度传感器包括信号延迟装置，比较装置，乘法器和计数装置。 信号延迟装置被配置为接收步进信号，根据温度程度对所接收的步进信号执行相位延迟操作，从而形成第一输出信号。 比较装置被配置为接收第一输出信号和阶跃信号，并相应地输出第二输出信号。 乘法器被配置为接收第二输出信号和时钟信号，并因此输出第三输出信号。 计数装置被配置为接收第三输出信号，对第三输出信号的脉冲数进行计数，并相应地生成数字代码。

公开(公告)号：US08588020B2

公开(公告)日：2013-11-19

申请号：US13297362

申请日：2011-11-16

申请人： Shi-Wen Chen

发明人： Shi-Wen Chen

IPC分类号： G11C7/02

CPC分类号： G11C7/08

摘要： A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.

摘要翻译： 提供了一种用于确定位线对上的电压值的读出放大器和方法。 读出放大器包括第一延迟链和第二延迟链。 第一延迟链电连接到位线并且被配置为在位线上接收时钟信号和第一电压，以便根据第一电压延迟时钟信号，并相应地产生第一延迟信号。 第二延迟链电连接到互补位线并且被配置为在互补位线上接收时钟信号和第二电压，以便根据第二电压延迟时钟信号，并相应地产生第二延迟信号。

公开(公告)号：US08493806B1

公开(公告)日：2013-07-23

申请号：US13342253

申请日：2012-01-03

申请人： Shi-Wen Chen

发明人： Shi-Wen Chen

IPC分类号： G11C7/02

CPC分类号： G11C7/06 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C29/026 ,  G11C29/028

摘要： A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

摘要翻译： 一种存储器的读出放大器电路，其包括读出放大器单元，第一开关单元和第二开关单元。 读出放大器单元由多个晶体管开关构成，具有第一，第二，第三和第四连接端子。 第一开关单元被配置为并联耦合在感测放大器单元的第一和第二连接端子之间。 第二开关单元被配置为并联耦合在读出放大器单元的第三和第四连接端子之间。 第一和第二开关单元各自由并联耦合的多个晶体管开关构成，并且被配置为控制第一和第二开关单元中的每个并联耦合的晶体管开关导通或关断，以便校准第一和第二开关单元的感测范围 读出放大器单元。 还提供了用于存储器的读出放大器电路的校准方法。

公开(公告)号：US20130124905A1

公开(公告)日：2013-05-16

申请号：US13297362

申请日：2011-11-16

申请人： Shi-Wen CHEN

发明人： Shi-Wen CHEN

IPC分类号： G06F1/10

CPC分类号： G11C7/08

摘要： A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.

摘要翻译： 提供了一种用于确定位线对上的电压值的读出放大器和方法。 读出放大器包括第一延迟链和第二延迟链。 第一延迟链电连接到位线并且被配置为在位线上接收时钟信号和第一电压，以便根据第一电压延迟时钟信号，并相应地产生第一延迟信号。 第二延迟链电连接到互补位线并且被配置为在互补位线上接收时钟信号和第二电压，以便根据第二电压延迟时钟信号，并相应地产生第二延迟信号。

公开(公告)号：US08970197B2

公开(公告)日：2015-03-03

申请号：US13565799

申请日：2012-08-03

申请人： Shi-Wen Chen

发明人： Shi-Wen Chen

IPC分类号： G05F1/00

CPC分类号： G05F3/08

摘要： A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage.

摘要翻译： 电压调节器电路包括多个晶体管和控制电路。 每个晶体管都有两个源极/漏极端子和一个栅极端子。 每个晶体管的一个源极/漏极端子电耦合到源极电压，并且晶体管的另一个源极/漏极端子彼此电耦合并且统称为电压调节器电路的输出端子。 控制电路电耦合到晶体管的栅极端子，并且被配置为根据输出端子处的电压与预定参考电压之间的差来确定要导通的晶体管的数量。

公开(公告)号：US20130170309A1

公开(公告)日：2013-07-04

申请号：US13342253

申请日：2012-01-03

申请人： Shi-Wen CHEN

发明人： Shi-Wen CHEN

IPC分类号： G11C7/06 ,  H03F3/45

CPC分类号： G11C7/06 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C29/026 ,  G11C29/028

摘要： A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

摘要翻译： 一种存储器的读出放大器电路，其包括读出放大器单元，第一开关单元和第二开关单元。 感测放大器单元由多个晶体管开关构成，具有第一，第二，第三和第四连接端子。 第一开关单元被配置为并联耦合在感测放大器单元的第一和第二连接端子之间。 第二开关单元被配置为并联耦合在读出放大器单元的第三和第四连接端子之间。 第一和第二开关单元各自由并联耦合的多个晶体管开关构成，并且被配置为控制第一和第二开关单元中的每个并联耦合的晶体管开关导通或关断，以便校准第一和第二开关单元的感测范围 读出放大器单元。 还提供了用于存储器的读出放大器电路的校准方法。

公开(公告)号：US08419274B2

公开(公告)日：2013-04-16

申请号：US12910199

申请日：2010-10-22

申请人： Shi-Wen Chen ,  Ming-Hung Chang ,  Wei-Chih Hsieh ,  Wei Hwang

发明人： Shi-Wen Chen ,  Ming-Hung Chang ,  Wei-Chih Hsieh ,  Wei Hwang

IPC分类号： G01K7/00

CPC分类号： G01K7/01 ,  G01K2219/00

摘要： A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.

摘要翻译： 完全片上的温度，过程和电压传感器包括电压传感器，过程传感器和温度传感器。 温度传感器包括偏置电流发生器，环形振荡器，固定脉冲发生器，与门和第一计数器。 偏置电流发生器根据芯片的工作电压产生与温度相关的输出电流。 环形振荡器根据输出电流产生振荡信号。 固定脉冲发生器产生固定的脉冲信号。 与门连接到环形振荡器和固定脉冲发生器，用于对振荡信号和固定脉冲信号进行逻辑与运算，并产生温度传感器信号。