公开(公告)号：US20100001942A1

公开(公告)日：2010-01-07

申请号：US12437110

申请日：2009-05-07

Applicant: TSUNG CHENG LIN ,  SHYH FENG CHEN ,  SHIH CHYN LIN ,  HSIANG PIN FAN ,  KUEI SHENG TSENG

Inventor： TSUNG CHENG LIN ,  SHYH FENG CHEN ,  SHIH CHYN LIN ,  HSIANG PIN FAN ,  KUEI SHENG TSENG

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0443 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2320/0247

Abstract: A liquid crystal display device comprises a pixel matrix including a plurality of subpixels, wherein the voltage polarities of two horizontal adjacent subpixels are opposite to one another, and the voltage polarity of one subpixel in four serial subpixels along a diagonal direction is opposite to the voltage polarities of the other three subpixels.

Abstract translation: 液晶显示装置包括：包括多个子像素的像素矩阵，其中两个水平相邻子像素的电压极性彼此相反，并且沿对角线方向的四个串行子像素中的一个子像素的电压极性与电压 其他三个子像素的极性。

公开(公告)号：US20120062534A1

公开(公告)日：2012-03-15

申请号：US13150388

申请日：2011-06-01

Applicant: Wei-Jen KAO ,  Shao-Chun Cheng ,  Chuo-Hsien Lin ,  Ming-Chang Shih ,  Chia-Kong Huang ,  Wen-Pin Chen ,  Shih-Chyn Lin

Inventor： Wei-Jen KAO ,  Shao-Chun Cheng ,  Chuo-Hsien Lin ,  Ming-Chang Shih ,  Chia-Kong Huang ,  Wen-Pin Chen ,  Shih-Chyn Lin

IPC: G09G5/00 ,  H03L5/00

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2330/028 ,  G09G2330/04

Abstract: A compensation circuitry of gate driving pulse signal is adapted to receive a gate driving pulse signal and includes a pre-processing circuit, a peak detector, a discharge circuit, a voltage buffer and a charge pump circuit. The pre-preprocessing circuit performs a pre-processing operation to the gate driving pulse signal to adjust a voltage thereof. The pre-processed gate driving pulse signal then is transmitted to the peak detector for obtaining a peak voltage after a charging operation, and also is transmitted to the discharge circuit to determine whether to enable the discharge circuit so that providing the peak detector with a discharge loop when the discharge circuit is enabled. The charge pump circuit acquires the peak voltage through the voltage buffer and then modulates a waveform of the gate driving pulse signal according to the peak voltage. A display device using the above compensation circuitry also is provided.

Abstract translation: 栅极驱动脉冲信号的补偿电路适于接收栅极驱动脉冲信号，并且包括预处理电路，峰值检测器，放电电路，电压缓冲器和电荷泵电路。 预处理电路对栅极驱动脉冲信号进行预处理操作，以调整其电压。 然后将预处理的栅极驱动脉冲信号传输到峰值检测器，以获得充电操作之后的峰值电压，并且还将其发送到放电电路以确定是否使能放电电路，使得为峰值检测器提供放电 当放电电路使能时回路。 电荷泵电路通过电压缓冲器获取峰值电压，然后根据峰值电压调制栅极驱动脉冲信号的波形。 还提供了使用上述补偿电路的显示装置。

公开(公告)号：US08098791B2

公开(公告)日：2012-01-17

申请号：US12789622

申请日：2010-05-28

Applicant: Shih-Chyn Lin ,  Hsiang-Pin Fan ,  Wen-Pin Chen ,  Kuei-Sheng Tseng ,  Chen-Yi Wu

Inventor： Shih-Chyn Lin ,  Hsiang-Pin Fan ,  Wen-Pin Chen ,  Kuei-Sheng Tseng ,  Chen-Yi Wu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled.

Abstract translation: 移位寄存器包括控制电路，上拉电路和下拉电路。 控制电路在启用期间根据起始脉冲信号产生控制信号。 上拉电路在由控制信号启用期间根据时钟信号产生门脉冲信号。 上拉电路包括双栅极晶体管。 双栅极晶体管的第一栅极电耦合到控制信号，双栅极晶体管的第二栅极电耦合到预定电压，双栅极晶体管的源极/漏极用作输出端 门脉冲信号和双栅极晶体管的漏极/源极电耦合到时钟信号。 下拉电路在第一个栅极处引起电位，而在上拉电路期间，输出端子处的另一个电位下降到电源电位。

公开(公告)号：US20090109389A1

公开(公告)日：2009-04-30

申请号：US12021244

申请日：2008-01-28

Applicant: Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

Inventor： Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

IPC: G02F1/1343

CPC classification number: G02F1/13624 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2320/028 ,  G09G2320/0673

Abstract: A pixel structure electrically connected to a scan line and a data line is provided. The pixel structure includes an active device, a first pixel electrode, a mean potential equilibrium circuit, and a second pixel electrode. The active device is electrically connected to the scan line and the data line. The first pixel electrode is electrically connected to the active device. The mean potential equilibrium circuit is electrically connected to the scan line and the data line. The second pixel electrode is electrically connected to the mean potential equilibrium circuit.

Abstract translation: 提供电连接到扫描线和数据线的像素结构。 像素结构包括有源器件，第一像素电极，平均电位平衡电路和第二像素电极。 有源器件电连接到扫描线和数据线。 第一像素电极电连接到有源器件。 平均电位平衡电路电连接到扫描线和数据线。 第二像素电极电连接到平均电位平衡电路。

公开(公告)号：US07990485B2

公开(公告)日：2011-08-02

申请号：US12021244

申请日：2008-01-28

Applicant: Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

Inventor： Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

IPC: G02F1/136 ,  G02F1/1343

CPC classification number: G02F1/13624 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2320/028 ,  G09G2320/0673

Abstract: A pixel structure electrically connected to a scan line and a data line is provided. The pixel structure includes an active device, a first pixel electrode, a mean potential equilibrium circuit, and a second pixel electrode. The active device is electrically connected to the scan line and the data line. The first pixel electrode is electrically connected to the active device. The mean potential equilibrium circuit is electrically connected to the scan line and the data line. The second pixel electrode is electrically connected to the mean potential equilibrium circuit.

Abstract translation: 提供电连接到扫描线和数据线的像素结构。 像素结构包括有源器件，第一像素电极，平均电位平衡电路和第二像素电极。 有源器件电连接到扫描线和数据线。 第一像素电极电连接到有源器件。 平均电位平衡电路电连接到扫描线和数据线。 第二像素电极电连接到平均电位平衡电路。

公开(公告)号：US20110150169A1

公开(公告)日：2011-06-23

申请号：US12789622

申请日：2010-05-28

Applicant: Shih-Chyn LIN ,  Hsiang-Pin Fan ,  Wen-Pin Chen ,  Kuei-Sheng Tseng ,  Chen-Yi Wu

Inventor： Shih-Chyn LIN ,  Hsiang-Pin Fan ,  Wen-Pin Chen ,  Kuei-Sheng Tseng ,  Chen-Yi Wu

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled

Abstract translation: 移位寄存器包括控制电路，上拉电路和下拉电路。 控制电路在启用期间根据起始脉冲信号产生控制信号。 上拉电路在由控制信号启用期间根据时钟信号产生门脉冲信号。 上拉电路包括双栅极晶体管。 双栅极晶体管的第一栅极电耦合到控制信号，双栅极晶体管的第二栅极电耦合到预定电压，双栅极晶体管的源极/漏极用作输出端 门脉冲信号和双栅极晶体管的漏极/源极电耦合到时钟信号。 下拉电路在第一个栅极处拉电位，而在上拉电路期间，输出端子处的另一个电位下降到电源电位被禁止

公开(公告)号：US08531374B2

公开(公告)日：2013-09-10

申请号：US13150388

申请日：2011-06-01

Applicant: Wei-Jen Kao ,  Shao-Chun Cheng ,  Chuo-Hsien Lin ,  Ming-Chang Shih ,  Chia-Kong Huang ,  Wen-Pin Chen ,  Shih-Chyn Lin

Inventor： Wei-Jen Kao ,  Shao-Chun Cheng ,  Chuo-Hsien Lin ,  Ming-Chang Shih ,  Chia-Kong Huang ,  Wen-Pin Chen ,  Shih-Chyn Lin

IPC: G09G3/36

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2330/028 ,  G09G2330/04

Abstract: A compensation circuitry of gate driving pulse signal is adapted to receive a gate driving pulse signal and includes a pre-processing circuit, a peak detector, a discharge circuit, a voltage buffer and a charge pump circuit. The pre-preprocessing circuit performs a pre-processing operation to the gate driving pulse signal to adjust a voltage thereof. The pre-processed gate driving pulse signal then is transmitted to the peak detector for obtaining a peak voltage after a charging operation, and also is transmitted to the discharge circuit to determine whether to enable the discharge circuit so that providing the peak detector with a discharge loop when the discharge circuit is enabled. The charge pump circuit acquires the peak voltage through the voltage buffer and then modulates a waveform of the gate driving pulse signal according to the peak voltage. A display device using the above compensation circuitry also is provided.

Abstract translation: 栅极驱动脉冲信号的补偿电路适于接收栅极驱动脉冲信号，并且包括预处理电路，峰值检测器，放电电路，电压缓冲器和电荷泵电路。 预处理电路对栅极驱动脉冲信号进行预处理操作，以调整其电压。 然后将预处理的栅极驱动脉冲信号传输到峰值检测器，以获得充电操作之后的峰值电压，并且还将其发送到放电电路以确定是否使能放电电路，使得为峰值检测器提供放电 当放电电路使能时回路。 电荷泵电路通过电压缓冲器获取峰值电压，然后根据峰值电压调制栅极驱动脉冲信号的波形。 还提供了使用上述补偿电路的显示装置。

公开(公告)号：US20080158745A1

公开(公告)日：2008-07-03

申请号：US11754970

申请日：2007-05-29

Applicant: Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

Inventor： Shyh-Feng Chen ,  Tsung-Cheng Lin ,  Shih-Chyn Lin

IPC: H02H9/04 ,  H02H9/02

CPC classification number: G09G3/3688 ,  G09G3/20 ,  G09G2320/0209 ,  G09G2330/021 ,  G09G2330/08

Abstract: Data transmission circuit with ESD protection comprises a first set of data lines and a second set of data lines; a first set of ESD protection components coupled to the first set of data lines; a second set of ESD protection components coupled to the second set of data lines; a first current path coupled to the first set of ESD protection components for dispensing the ESD current; and a second current path coupled to the second set of ESD protection components for dispensing the ESD current.

Abstract translation: 具有ESD保护的数据传输电路包括第一组数据线和第二组数据线; 耦合到第一组数据线的第一组ESD保护组件; 耦合到所述第二组数据线的第二组ESD保护组件; 第一电流通路，耦合到用于分配ESD电流的第一组ESD保护部件; 以及耦合到第二组ESD保护组件以分配ESD电流的第二电流通路。