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公开(公告)号:US09245071B2
公开(公告)日:2016-01-26
申请号:US13407241
申请日:2012-02-28
申请人: Isadore T. Katz , Joao M. Geada , Leon LaFrance , Ferenc Varadi , Ahran Dunsmoor , James Kuzeja , Shiva Raja
发明人: Isadore T. Katz , Joao M. Geada , Leon LaFrance , Ferenc Varadi , Ahran Dunsmoor , James Kuzeja , Shiva Raja
CPC分类号: G06F17/5031
摘要: A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.
摘要翻译: 电路设计的定时分析方法包括对于电路设计中的单元库的单元的一个或多个实例的每组,根据设计中的组的电路上下文确定该组的定时相关数据。 上下文包括路径深度,输出负载和输入转换速率中的至少一个。 应用确定的定时相关数据分析电路设计。
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公开(公告)号:US20130227510A1
公开(公告)日:2013-08-29
申请号:US13407241
申请日:2012-02-28
申请人: Isadore T. Katz , Joao M. Geada , Leon LaFrance , Ferenc Varadi , Ahran Dunsmoor , James Kuzeja , Shiva Raja
发明人: Isadore T. Katz , Joao M. Geada , Leon LaFrance , Ferenc Varadi , Ahran Dunsmoor , James Kuzeja , Shiva Raja
IPC分类号: G06F17/50
CPC分类号: G06F17/5031
摘要: A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.
摘要翻译: 电路设计的定时分析方法包括对于电路设计中的单元库的单元的一个或多个实例的每组,根据设计中的组的电路上下文确定该组的定时相关数据。 上下文包括路径深度,输出负载和输入转换速率中的至少一个。 应用确定的定时相关数据分析电路设计。
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公开(公告)号:US07761826B1
公开(公告)日:2010-07-20
申请号:US11782619
申请日:2007-07-24
申请人: Venkat Thanvantri , Shiva Raja , Igor Keller , Lizheng Zhang
发明人: Venkat Thanvantri , Shiva Raja , Igor Keller , Lizheng Zhang
IPC分类号: G06F17/50
CPC分类号: G06F17/5036
摘要: Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.
摘要翻译: 与统计串扰路径延迟模型相关的串扰分析方法和系统,适用于现有的静态时序框架,性能和容量的开销很小。 使用更逼真的模型或假设,而不是更积极和不太可能的确定性模型。
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