公开(公告)号：US07873928B2

公开(公告)日：2011-01-18

申请号：US12472323

申请日：2009-05-26

Applicant: Po-Hung Lin ,  Wei-Chung Chao ,  Shyh-Chang Lin

Inventor： Po-Hung Lin ,  Wei-Chung Chao ,  Shyh-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.

Abstract translation: 放置工具通过首先定义约束组的多级分层结构来产生经受设备匹配，对称和接近约束的模拟集成电路（IC）内的多个设备模块的最佳布置，其中每个约束组由元件 它们受到一个布局限制。 每个约束组的每个元素由设备模块中的一个或位于层次结构的较低级别的约束组中的另一个组成。 该工具然后生成用于IC的试验放置的分层B *树表示，其包括表示层级的每个约束组的单独节点，以及不包括在任何约束组中的每个设备模块的单独节点。 表示约束组的每个节点定义了每个设备模块或组成与约束组上的放置约束一致的约束组的下级约束组的IC内的相对位置。 放置工具迭代地扰乱分层B *树，以产生IC设计的试验放置序列，然后评估每个试验放置的成本函数，以选择最佳的试验放置作为最佳试验放置。

公开(公告)号：US07603640B2

公开(公告)日：2009-10-13

申请号：US11550487

申请日：2006-10-18

Applicant: Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

Inventor： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

Abstract translation: 为了生成由网络互连的模块的集合形成的集成电路的平面图，将由集成电路占据的楼层空间划分为区域，并且所有模块都被分配在这些区域中。 然后将区域迭代地划分成更小的逐渐变小的区域，其中模块先前分配了在其被分割的区域中分配的任何分区，直到布局图的每个区域已经被分配不超过预定的最大数量的模块。 然后为每个区域生成单独的平面图。 然后迭代地合并相邻区域以创建逐渐更大的区域，直到仅剩下一个区域，其中在合并任何相邻区域以形成更大的合并区域时，相邻区域的平面图被合并和细化以创建合并区域的平面图 。

公开(公告)号：US20090235219A1

公开(公告)日：2009-09-17

申请号：US12472323

申请日：2009-05-26

Applicant: Po-Hung LIN ,  Wei-Chung CHAO ,  Shyh-Chang LIN

Inventor： Po-Hung LIN ,  Wei-Chung CHAO ,  Shyh-Chang LIN

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.

Abstract translation: 放置工具通过首先定义约束组的多级分层结构来产生经受设备匹配，对称和接近约束的模拟集成电路（IC）内的多个设备模块的最佳布置，其中每个约束组由元件 它们受到一个布局限制。 每个约束组的每个元素由设备模块中的一个或位于层次结构的较低级别的约束组中的另一个组成。 该工具然后生成用于IC的试验放置的分层B *树表示，其包括表示层级的每个约束组的单独节点，以及不包括在任何约束组中的每个设备模块的单独节点。 表示约束组的每个节点定义了每个设备模块或组成与约束组上的放置约束一致的约束组的下级约束组的IC内的相对位置。 放置工具迭代地扰乱分层B *树，以产生IC设计的试验放置序列，然后评估每个试验放置的成本函数，以选择最佳的试验放置作为最佳试验放置。

公开(公告)号：US20080155485A1

公开(公告)日：2008-06-26

申请号：US11550487

申请日：2006-10-18

Applicant: Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

Inventor： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

Abstract translation: 为了生成由网络互连的模块的集合形成的集成电路的平面图，将由集成电路占据的楼层空间划分为区域，并且所有模块都被分配在这些区域中。 然后将区域迭代地划分成更小的逐渐变小的区域，其中模块先前分配了在其被分割的区域中分配的任何分区，直到布局图的每个区域已经被分配不超过预定的最大数量的模块。 然后为每个区域生成单独的平面图。 然后迭代地合并相邻区域以创建逐渐更大的区域，直到仅剩下一个区域，其中在合并任何相邻区域以形成更大的合并区域时，相邻区域的平面图被合并和细化以创建合并区域的平面图 。

公开(公告)号：US07386823B2

公开(公告)日：2008-06-10

申请号：US11186165

申请日：2005-07-20

Applicant: Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

Inventor： Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic diagram of symbols representing devices forming the pattern. The generator identifies each set of devices in the netlist that exhibits any rule's interconnection pattern as a separate “soft group”, places a constraint consistent with the rule on relative positioning within the schematic diagram of symbols representing the soft group, resolves any constraint conflicts in accordance with a constraint resolution scheme, and then places all device symbols in the schematic diagram in a manner consistent accordance with the constraints.

Abstract translation: 示意图生成器处理网表以基于一组对应于互连设备的单独特征模式的布局规则生成示意图，并且在表示形成该图案的设备的符号的示意图中指定对相对位置的约束。 生成器将网表中的任何规则的互连模式的每组设备识别为单独的“软组”，将表示软组的符号的示意图中的规则与规则相对应的相对定位放置在约束冲突中 根据约束解决方案，然后以符合约束的方式将所有设备符号放置在原理图中。

公开(公告)号：US20070256045A1

公开(公告)日：2007-11-01

申请号：US11681859

申请日：2007-03-05

Applicant: Shyh-Chang Lin ,  Tai-Chen Chen ,  Yao-Wen Chang ,  Feng-Yuan Chang

Inventor： Shyh-Chang Lin ,  Tai-Chen Chen ,  Yao-Wen Chang ,  Feng-Yuan Chang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A router selects routes for nets interconnecting terminals of circuit devices within an area of an IC. The router organizes the IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary that is a probabilistic measure of an estimated percentage of a capacity of the GRC boundary that will be occupied by nets when all nets have been routed. The router then iteratively partitions the IC area into progressively smaller tiles until the tiles reach a predetermined minimum size. Between partitioning iterations, the router selects a route for each net passing between tiles when possible to do so without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles. Between merging iterations, the router selects a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting a route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries and then modifies the congestion map to reflect changes in routing probabilities occasioned by the route selection before choosing a route for any other connection.

Abstract translation: 路由器选择IC内的电路设备的互连终端的网络路由。 路由器将IC区域组织成全局路由信元（GRC）阵列，并生成拥塞映射，为每个GRC边界提供单独的拥塞因子，这是对将被占用的GRC边界的容量的估计百分比的概率测量 当所有的网络都被路由时，通过网络。 然后路由器将IC区域迭代地分割成逐渐变小的瓦片，直到瓦片达到预定的最小尺寸。 在分区迭代之间，路由器为可能的每个网络选择一个路由，以便在不改变任何先前路由的网络的情况下进行。 之后路由器迭代地将瓦片合并成逐渐变大的瓦片。 在合并迭代之间，路由器选择一个完全位于单个瓦片内的每个先前未被路由的网络的路由，在必要时更改先前路由网络的路由以适应所选择的路由。 当选择网络的任何连接的路由时，路由器寻求将所有GRC边界的拥塞因素的成本函数最小化，然后修改拥塞映射以反映路由选择引起的路由概率的变化，然后选择任何其他路由 连接。

公开(公告)号：US20060090152A1

公开(公告)日：2006-04-27

申请号：US10975151

申请日：2004-10-27

Applicant: Po-Hung Lin ,  Shyh-Chang Lin

Inventor： Po-Hung Lin ,  Shyh-Chang Lin

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/50 ,  G06F2217/74

Abstract: A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram. When the user requests a pan operation to shift the display to another portion of the schematic diagram, the system determines routes for representations of nets that are to reside in that other portion of the schematic diagram and then displays those net representations upon panning to that other portion of the schematic diagram

Abstract translation: 用于处理电路的网表描述的系统以生成包括单元和网的表示的示意图的显示，首先确定示意图中单元实例表示的位置，然后显示示意图，包括单元实例表示但不包括 网的表示。 当用户请求放大操作以便以可以查看网络表示的比例显示原理图的较小部分时，系统确定要驻留在原理图的该部分中的网络的表示的路由，然后显示 放大到原理图的那部分时的这些净表示。 当用户请求平移操作将显示器移动到原理图的另一部分时，系统确定要驻留在原理图的该其他部分的网络的表示的路由，然后在平移到另一个网络时显示这些网络表示 部分原理图

公开(公告)号：US07739646B2

公开(公告)日：2010-06-15

申请号：US11839042

申请日：2007-08-15

Applicant: Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

Inventor： Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

Abstract translation: 基于计算机的放置和布线（P＆R）工具存储一组电路图案，每个电路图案通过参考设备组的每个设备并通过指示通过网络将形成被引用设备的设备元件相互连接来描述单独的设备组，一组 布置图案，每个提供用于放置形成由对应的一个电路图案描述的设备组的IC设备元件和一组路由样式的引导件，以用作在放置在特定图案中的设备元件之间布线网络的引导。 为了产生由网表描述的模拟IC的布局，P＆R工具识别IC中的每组设备，形成由任何电路图形描述的设备组。 然后，P＆R工具为每个识别的设备组生成单独的设备组布局，使用放置模式作为在设备组布局中放置设备元素的引导，并使用路由样式作为在设备组布局中互连设备元素的路由网络的引导。 P＆R工具还为未包含在任何识别的设备组中的每个设备生成布局。 然后，该工具生成包含每个生成的设备和设备组布局的IC的布局。

公开(公告)号：US07707536B2

公开(公告)日：2010-04-27

申请号：US11681859

申请日：2007-03-05

Applicant: Shyh-Chang Lin ,  Tai-Chen Chen ,  Yao-Wen Chang ,  Feng-Yuan Chang

Inventor： Shyh-Chang Lin ,  Tai-Chen Chen ,  Yao-Wen Chang ,  Feng-Yuan Chang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selecting a route for each net passing between tiles when possible without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles while selecting a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting each route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries.

Abstract translation: 路由器将IC区域组织成全局路由信元（GRC）阵列，并产生拥塞映射，为每个GRC边界提供单独的拥塞因子。 然后路由器然后迭代地将IC区域分割成逐渐变小的瓦片，同时在可能的情况下为每个网络之间传递每个网络的路由而不改变任何先前路由的网络。 然后，路由器将块逐次合并为逐渐变大的瓦片，同时为完全在单个瓦片内的每个先前未被路由的网络选择路由，在必要时改变先前路由网络的路由以适应所选择的路由。 当选择网络的任何连接的每个路由时，路由器寻求最小化所有GRC边界的拥塞因素的成本函数。

公开(公告)号：US07178123B2

公开(公告)日：2007-02-13

申请号：US10975151

申请日：2004-10-27

Applicant: Po-Hung Lin ,  Shyh-Chang Lin

Inventor： Po-Hung Lin ,  Shyh-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F2217/74

Abstract: A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram. When the user requests a pan operation to shift the display to another portion of the schematic diagram, the system determines routes for representations of nets that are to reside in that other portion of the schematic diagram and then displays those net representations upon panning to that other portion of the schematic diagram.

Abstract translation: 用于处理电路的网表描述的系统以生成包括单元和网的表示的示意图的显示，首先确定示意图中单元实例表示的位置，然后显示示意图，包括单元实例表示但不包括 网的表示。 当用户请求放大操作以便以可以查看网络表示的比例显示原理图的较小部分时，系统确定要驻留在原理图的该部分中的网络的表示的路由，然后显示 放大到原理图的那部分时的这些净表示。 当用户请求平移操作将显示器移动到原理图的另一部分时，系统确定要驻留在原理图的其他部分的网络的表示的路由，然后在平移到另一个网络时显示这些网络表示 部分原理图。