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    Computer Aided Design Model Conversion
    1.
    发明申请
    Computer Aided Design Model Conversion 审中-公开

    公开(公告)号：US20190205482A1

    公开(公告)日：2019-07-04

    申请号：US15859061

    申请日：2017-12-29

    申请人： Luther Walke

    发明人： Luther Walke

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G06F2217/02 ,  G06F2217/04 ,  G06F2217/74

    摘要： Techniques which may allow computer-aided design (CAD) conversion are described. In one implementation, CAD conversion may convert all objects placed in a 3D CAD model via a customized symbol into an object independent of that symbol, or in the case of parametric symbols, the user-defined form utilized for its placement. CAD conversion may also remove all constructions associated with the utilization of that symbol from any databases or files associated with the 3D CAD model.

    Custom Piecewise Digital Layout Generation
    4.
    发明申请
    Custom Piecewise Digital Layout Generation 审中-公开

    公开(公告)号：US20190042687A1

    公开(公告)日：2019-02-07

    申请号：US15667381

    申请日：2017-08-02

    申请人： Oracle International Corporation

    发明人： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness ,  Johan Bastiaens

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/74

    摘要： A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

    Integrated circuit modeling method using resistive capacitance information
    5.
    发明授权
    Integrated circuit modeling method using resistive capacitance information 有权

    公开(公告)号：US09996643B2

    公开(公告)日：2018-06-12

    申请号：US14543352

    申请日：2014-11-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Ching-Shun Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/5045 ,  G06F2217/74

    摘要： A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

    Method and system for displaying waveform results directly on a schematic
    6.
    发明授权
    Method and system for displaying waveform results directly on a schematic 有权

    公开(公告)号：US09858374B1

    公开(公告)日：2018-01-02

    申请号：US15165334

    申请日：2016-05-26

    申请人： Cadence Design Systems, Inc.

    发明人： John Purchase ,  Ian Gebbie

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5036 ,  G06F17/5063 ,  G06F2217/74

    摘要： An improved approach is provided to displaying waveform data, where a schematic and corresponding waveform data can be displayed directly on a schematic of an electronic circuit. By providing both the schematic and waveform results in a same display, circuit designers and verification engineers are given more control over their working environments and can more efficiently utilize available data including the schematic and the waveform data. Furthermore, results can be pinned to a relevant net to which those results correspond providing circuit designers and verification engineers with an ability to view only the available data they wish to view, and to do so in a context of the electronic circuit itself on the schematic.

    Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations
    7.
    发明授权
    Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations 有权

    公开(公告)号：US09779193B1

    公开(公告)日：2017-10-03

    申请号：US14675665

    申请日：2015-03-31

    申请人： Cadence Design Systems, Inc.

    发明人： Arnold Ginetti ,  Yuan-Kai Pei ,  Yu-Chi Su

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/74

    摘要： Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.

    Simulating performance, reliability, weight, and cost using a physical model
    8.
    发明授权
    Simulating performance, reliability, weight, and cost using a physical model 有权

    公开(公告)号：US09760662B1

    公开(公告)日：2017-09-12

    申请号：US15155376

    申请日：2016-05-16

    申请人： XLDyn, LLC

    发明人： Kong Ping Oh ,  Thomas Tecco

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F2217/74

    摘要： Measures of effectiveness (MoEs) of a system, including MoEs derived from physical variables and MoEs derived from non-physical variables, can be calculated using a single model using the same software system and the same set of data. Setting up and performance of trade-off studies may be facilitated. Data needed for simulation, including physical attributes such as inertia and spring rate and non-physical attributes such as cost, weight, and mean time between failures, may be persisted in the same manner. Different topologies may be created from the same model. A physical topology may include information that may be used to generate the governing systems equations based on laws of physics. A conceptual topology may include non-physical information, such as weight and cost information, and information that may be used to generate the governing systems equations based on probabilistic principles.

    Configurable composite connector
    9.
    发明授权
    Configurable composite connector 有权

    公开(公告)号：US09697304B1

    公开(公告)日：2017-07-04

    申请号：US13433066

    申请日：2012-03-28

    申请人： Jeffrey M. Wendlandt ,  Andrew C. Bennett

    发明人： Jeffrey M. Wendlandt ,  Andrew C. Bennett

    IPC分类号： G06F7/60 ,  G06F17/10 ,  G06F17/50

    CPC分类号： G06F17/5009 ,  G06F2217/16 ,  G06F2217/74

    摘要： A graphical model may include a plurality of graphical objects representing physical elements, and connections between graphical objects may be represented by physical connection lines. A set of physical connections between two or more graphical objects may be configured as belonging to a group. A switching unit may toggle the graphical model between a single-line display mode and a multi-line display mode. In the multi-line display mode, each of the individual physical connection lines linking two or more graphical objects are displayed in the model. In response to user or other input, the switching unit may redraw the graphical model in single line mode in which the individual physical connections configured as a group are replaced with a single, composite connection line. The graphical model may be executable to simulate the physical system, and the execution may be unaffected by the display mode.

    Systems And Methods For Binding Mismatched Schematic And Layout Design Hierarchy
    10.
    发明申请
    Systems And Methods For Binding Mismatched Schematic And Layout Design Hierarchy 有权

    公开(公告)号：US20170124235A1

    公开(公告)日：2017-05-04

    申请号：US14981422

    申请日：2015-12-28

    申请人： CADENCE DESIGN SYSTEMS, INC.

    发明人： Kenneth Ferguson ,  Jean-Marc Bourguet

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/04 ,  G06F2217/74

    摘要： Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.