公开(公告)号：US20210407996A1

公开(公告)日：2021-12-30

申请号：US16913333

申请日：2020-06-26

Applicant: Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

Inventor： Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires.