公开(公告)号：US20210407996A1

公开(公告)日：2021-12-30

申请号：US16913333

申请日：2020-06-26

申请人： Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

发明人： Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

申请人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

发明人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200098921A1

公开(公告)日：2020-03-26

申请号：US16143222

申请日：2018-09-26

申请人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

发明人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

摘要： Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20160204110A1

公开(公告)日：2016-07-14

申请号：US14912402

申请日：2013-09-25

申请人： Rajashree BASKARAN ,  Kimin JUN ,  Patrick MORROW

发明人： Rajashree Baskaran ,  Kimin JUN ,  Patrick MORROW

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10832 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/20 ,  H01L28/87 ,  H01L28/91 ,  H01L29/945

摘要： Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

摘要翻译： 描述了在器件层下形成无源元件的方法。 这些方法和结构可以包括在衬底中形成至少一个无源结构，例如电容器和电阻器结构，其中被动结构垂直地设置在衬底内。 绝缘体层形成在无源结构的顶表面上，在绝缘体层上形成器件层，并且形成接触件以将布置在器件层中的器件耦合到至少一个被动结构。