公开(公告)号：US6072335A

公开(公告)日：2000-06-06

申请号：US972791

申请日：1997-11-18

申请人： Peter William Hughes

发明人： Peter William Hughes

IPC分类号： H04N9/64 ,  G05F3/24 ,  H03K5/151 ,  H03K17/042 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/0185

CPC分类号： G05F3/24 ,  H03K17/04206 ,  H03K17/167 ,  H03K5/151

摘要： An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

摘要翻译： 输出电流单元包括具有连接在电压供应线和互补输出之间的第一晶体管的共源共栅电路。 第二和第三晶体管由在输出节点和接地线之间具有并联导电路径的反相器电路控制，并联导电路径具有与控制电路不同的载流能力，以切换电流承载路径中较强的电流。

公开(公告)号：US07100138B2

公开(公告)日：2006-08-29

申请号：US10863333

申请日：2004-06-09

申请人： Neal Fitzhenry ,  Peter William Hughes ,  Simon Christopher Dequin Clemow ,  Paul Andrew Freeman

发明人： Neal Fitzhenry ,  Peter William Hughes ,  Simon Christopher Dequin Clemow ,  Paul Andrew Freeman

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.

公开(公告)号：US07266787B2

公开(公告)日：2007-09-04

申请号：US11067200

申请日：2005-02-24

申请人： Peter William Hughes ,  Shannon Vance Morton ,  Trevor Kenneth Monk

发明人： Peter William Hughes ,  Shannon Vance Morton ,  Trevor Kenneth Monk

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

摘要翻译： 公开了一种用于优化由标准单元（12）构建的半导体集成电路中的晶体管性能或定制晶体管级布局的方法（300）。 NMOS扩散的有源区域在两个相邻单元（112）之间的连接区域（102）延伸，在每个单元的相邻边缘处具有与扩散相同的网。 扩散区域扩展以限制有源和非活性界面的发生，以最小化晶格应变效应并提高晶体管性能。

公开(公告)号：US5812121A

公开(公告)日：1998-09-22

申请号：US397840

申请日：1995-03-02

申请人： Peter William Hughes

发明人： Peter William Hughes

IPC分类号： H04N9/64 ,  G05F3/24 ,  H03K5/151 ,  H03K17/042 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/0948 ,  H03M1/66

CPC分类号： G05F3/24 ,  H03K17/04206 ,  H03K17/167 ,  H03K5/151

摘要： An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

摘要翻译： 输出电流单元包括具有连接在电压供应线和互补输出之间的第一晶体管的共源共栅电路。 第二和第三晶体管由在输出节点和接地线之间具有并联导电路径的反相器电路控制，并联导电路径具有与控制电路不同的载流能力，以切换电流承载路径中较强的电流。

公开(公告)号：US06766503B2

公开(公告)日：2004-07-20

申请号：US10158000

申请日：2002-05-31

申请人： Neal Fitzhenry ,  Peter William Hughes ,  Simon Christopher Dequin Clemow ,  Paul Andrew Freeman

发明人： Neal Fitzhenry ,  Peter William Hughes ,  Simon Christopher Dequin Clemow ,  Paul Andrew Freeman

IPC分类号： G06F1750

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.

公开(公告)号：US07564274B2

公开(公告)日：2009-07-21

申请号：US11065904

申请日：2005-02-24

申请人： Peter William Hughes

发明人： Peter William Hughes

IPC分类号： H03K3/00

CPC分类号： H03K17/165

摘要： A system (10,90), apparatus (12,30,40,50,60,70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36,46) within a complementary MOS (CMOS) environment. A load control (32,42) is arranged as a compliment to the MOS transistor. A comparator (34,44) is electrically connected to the load control and the MOS transistor, and produces an output signal representative of the detection of a current leakage exceeding a threshold. In response to the received output signal indicating an excess current leakage, system voltage/frequency may be adjusted to prevent damage to the CMOS environment.

摘要翻译： 公开了一种系统（10,90），装置（12,30,40,50,60,70）和方法（100），用于检测金属氧化物半导体（MOS）晶体管（36）的漏极/源极之间的过剩电流泄漏， 46）在互补MOS（CMOS）环境中。 负载控制（32,42）被配置为对MOS晶体管的补充。 比较器（34,44）电连接到负载控制和MOS晶体管，并且产生表示超过阈值的电流泄漏检测的输出信号。 响应于接收的输出信号指示过大的电流泄漏，可以调节系统电压/频率以防止损坏CMOS环境。