公开(公告)号：US20100211858A1

公开(公告)日：2010-08-19

申请号：US12708323

申请日：2010-02-18

申请人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Bmv

发明人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Bmv

IPC分类号： H03M13/25 ,  G06F15/76 ,  G06F15/80 ,  G06F9/02 ,  G06F11/08 ,  H03M13/41

CPC分类号： H03M13/4169 ,  H03M13/256 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/6362

摘要： An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

摘要翻译： 一种应用专用处理器，用于实现用于接收符号的信道解码功能的维特比解码算法。 维特比解码算法是位串行解码算法和基于块的解码算法中的至少一种。 应用专用处理器包括执行加载存储功能的加载存储，逻辑和去穿孔（LLD）槽，逻辑功能，去穿孔功能和追踪地址生成功能，分支度量计算 （BMU）时隙，执行基数-2分支度量计算，基数-4分支度量计算和平方欧几里德分支度量计算，以及执行基数2路径度量计算的加法比较选择（ACS） 基数4路径度量计算，最佳状态计算和决策位生成。 LLD插槽，BMU插槽和ACS插槽以软件流水线方式执行，以实现高速维特比解码功能。