公开(公告)号：US20050188130A1

公开(公告)日：2005-08-25

申请号：US11112209

申请日：2005-04-22

申请人： Stacey Secatch

发明人： Stacey Secatch

IPC分类号： G06F3/00 ,  G06F5/06 ,  G06F13/00

CPC分类号： G06F5/065

摘要： The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

公开(公告)号：US06711716B1

公开(公告)日：2004-03-23

申请号：US10255285

申请日：2002-09-26

申请人： Brian Mueller ,  Stacey Secatch ,  James Hansen

发明人： Brian Mueller ,  Stacey Secatch ,  James Hansen

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F1/10 ,  H01L27/0203

摘要： A method for allowing in-place programming of clock buffer delays of clock buffers in an integrated circuit clock tree is presented. The clock tree comprises at least one clock driver connected between a clock driver input line and a clock driver output line. Each clock driver comprises a plurality of clock buffers connected in series between the clock driver input line and, potentially, the clock driver output line. Metal is reserved in intervening metal layers within a clock driver block between the clock driver input line and the input of a first one of said plurality of clock buffers in the variable clock buffer chain. Metal is reserved on one or more metal layers for connecting the output of each of the clock buffers in the clock buffer chain to the clock driver output line. The metal layers are partitioned into one or more programming layers and one or more non-programming layers. Then, for each clock buffer in the clock buffer chain, an output connection route is mapped between the output of the respective clock buffer to the clock driver output line through the plurality of metal layers. Metal corresponding to the output connection route is then implemented on each of said non-programming layers. During design, a desired clock driver delay for the clock driver is determined. Metal corresponding to the output connection route on each of said programming layers to connect the output of the clock buffer corresponding to the desired delay to the clock driver output line.

摘要翻译： 提出了一种用于允许在集成电路时钟树中的时钟缓冲器的时钟缓冲器延迟的就地编程的方法。 时钟树包括连接在时钟驱动器输入线和时钟驱动器输出线之间的至少一个时钟驱动器。 每个时钟驱动器包括串联连接在时钟驱动器输入线和潜在地时钟驱动器输出线之间的多个时钟缓冲器。 在时钟驱动器输入线和可变时钟缓冲器链中的所述多个时钟缓冲器中的第一个的输入之间的时钟驱动器块内的金属间隔保留有金属。 金属被保留在一个或多个金属层上，用于将时钟缓冲器链中的每个时钟缓冲器的输出连接到时钟驱动器输出线。 金属层被划分成一个或多个编程层和一个或多个非编程层。 然后，对于时钟缓冲器链中的每个时钟缓冲器，通过多个金属层将输出连接路由映射到各个时钟缓冲器的输出到时钟驱动器输出线之间。 然后在每个所述非编程层上实现对应于输出连接路由的金属。 在设计期间，确定时钟驱动器所需的时钟驱动器延迟。 对应于每个所述编程层上的输出连接路线的金属，以将对应于期望延迟的时钟缓冲器的输出连接到时钟驱动器输出线。

公开(公告)号：US07818699B1

公开(公告)日：2010-10-19

申请号：US11706440

申请日：2007-02-14

申请人： Russell Bryan Stuber ,  Stacey Secatch ,  Jason R. Lawley

发明人： Russell Bryan Stuber ,  Stacey Secatch ,  Jason R. Lawley

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The code set, which includes one or more parameter variables that determine the length and width of the implemented pipeline core, is synthesized by setting the parameter variables to selected constant values to generate a reduced netlist embodying a static circuit configuration for the implemented pipeline core.

摘要翻译： 通过提供体现代表流水线核心的动态电路配置的扩展网表的单个代码集来动态规定用于在可编程集成电路（IC）中实现的流水线核心的电路配置。 通过将参数变量设置为选定的常数值来合成代码集，其包括确定实现的流水线核心的长度和宽度的一个或多个参数变量，以产生体现实现的流水线核心的静态电路配置的减少的网表。

公开(公告)号：US07590965B1

公开(公告)日：2009-09-15

申请号：US11642179

申请日：2006-12-19

申请人： Michael George Ingoldby ,  James E. Ogden ,  Jeffrey C. Ward ,  Stacey Secatch ,  Restu I. Ismail ,  Thomas E. Fischaber

发明人： Michael George Ingoldby ,  James E. Ogden ,  Jeffrey C. Ward ,  Stacey Secatch ,  Restu I. Ismail ,  Thomas E. Fischaber

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

摘要翻译： 根据针对特定要求定制的设计架构生成PLD设计实现的方法。 PLD设计的硬件描述语言（HDL）描述包括将影响设计的首选实现的PLD设计的至少一个参数值。 该参数值被传递给高级语言（HLL）函数，用于根据目标应用程序的指定需求来确定定制的设计架构。 HLL函数返回指定定制设计架构的数据。 该数据用于生成遵循定制设计架构强加的约束的PLD设计的实现。 结果可以是例如PLD设计的逻辑门表示，设计的网表，或者在目标PLD中实现设计的比特流。

公开(公告)号：US07565465B2

公开(公告)日：2009-07-21

申请号：US11112209

申请日：2005-04-22

申请人： Stacey Secatch

发明人： Stacey Secatch

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F5/065

摘要： The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

摘要翻译： 本发明提供了一种推回FIFO架构，其使得能够在数据流的开始处将已经从FIFO中卸载的值推回到FIFO中，如果确定数据值不应该从FIFO中卸载 。 因此，推回的数据值将是在下一个读取周期从FIFO中卸载的第一个数据值。 因为不应该卸载的数据值不会丢失，并且被放置在数据值序列的开始处，所以推回FIFO使得能够执行来自FIFO的数据值的推测性卸载。

公开(公告)号：US08356125B1

公开(公告)日：2013-01-15

申请号：US12121642

申请日：2008-05-15

申请人： Stacey Secatch

发明人： Stacey Secatch

IPC分类号： G06F5/00

CPC分类号： G06F5/065

摘要： In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a first memory stage for storing a plurality of pointer values associated with a plurality of buffers, wherein the plurality of buffers is associated with a plurality of logical channels. The device further comprise a second memory stage, wherein an access address to the second memory stage is formed from a concatenation of one of the plurality of pointer values and a channel number corresponding to one of the plurality of logical channels.

摘要翻译： 在一个实施例中，公开了一种设备。 例如，在本发明的一个实施例中，该设备包括用于存储与多个缓冲器相关联的多个指针值的第一存储器级，其中多个缓冲器与多个逻辑通道相关联。 所述设备还包括第二存储器级，其中由所述多个指针值中的一个与所述多个逻辑信道之一相对应的通道号的级联形成到所述第二存储器级的存取地址。

公开(公告)号：US07668186B1

公开(公告)日：2010-02-23

申请号：US11369338

申请日：2006-03-07

申请人： Roscoe Conkling Nelson, IV ,  Stacey Secatch ,  Thomas E. Fischaber ,  Tony Viet Nam Le

发明人： Roscoe Conkling Nelson, IV ,  Stacey Secatch ,  Thomas E. Fischaber ,  Tony Viet Nam Le

IPC分类号： H04L12/56

CPC分类号： H04L49/90

摘要： A buffer management system for a data processing system can include a plurality of tokens wherein each token is associated with one of a plurality of buffers, and a plurality of first-in-first-out (FIFO) memories. Each FIFO memory can be associated with a stage of the data processing system and is configured to store at least one of the tokens. The buffer management system also can include control logic configured to determine a state of one or more selected buffers and transfer the token associated with the selected buffer from a source FIFO memory to a target FIFO memory. The target FIFO memory can be selected according to the state of the selected buffer.

摘要翻译： 用于数据处理系统的缓冲器管理系统可以包括多个令牌，其中每个令牌与多个缓冲器中的一个和多个先进先出（FIFO）存储器相关联。 每个FIFO存储器可以与数据处理系统的级相关联，并且被配置为存储至少一个令牌。 缓冲器管理系统还可以包括被配置为确定一个或多个所选择的缓冲器的状态并将与所选择的缓冲器相关联的令牌从源FIFO存储器传送到目标FIFO存储器的控制逻辑。 可以根据所选缓冲区的状态选择目标FIFO存储器。

公开(公告)号：US06941393B2

公开(公告)日：2005-09-06

申请号：US10091682

申请日：2002-03-05

申请人： Stacey Secatch

发明人： Stacey Secatch

IPC分类号： G06F3/00 ,  G06F5/06 ,  G06F13/00

CPC分类号： G06F5/065

摘要： The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

摘要翻译： 本发明提供了一种推回FIFO架构，其使得能够在数据流的开始处将已经从FIFO中卸载的值推回到FIFO中，如果确定数据值不应该从FIFO中卸载 。 因此，推回的数据值将是在下一个读取周期从FIFO中卸载的第一个数据值。 因为不应该卸载的数据值不会丢失，并且被放置在数据值序列的开始处，所以推回FIFO使得能够执行来自FIFO的数据值的推测性卸载。

公开(公告)号：US08667254B1

公开(公告)日：2014-03-04

申请号：US12121614

申请日：2008-05-15

申请人： Carl F. Rohrer ,  Patrick J. Smith ,  Stacey Secatch

发明人： Carl F. Rohrer ,  Patrick J. Smith ,  Stacey Secatch

IPC分类号： G06F15/163 ,  G06F15/80

CPC分类号： G06F15/167

摘要： In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

摘要翻译： 在一个实施例中，公开了一种网络设备。 例如，在本发明的一个实施例中，该设备包括处理器和具有接收缓冲器和发送缓冲器的核心存储器。 该设备包括耦合到处理器和核心存储器的总线。 该设备包括经由直接链路耦合到核心存储器的至少一个协处理器，其中所述至少一个协处理器能够在没有来自处理器的协助下访问以下中的至少一个：接收缓冲器或发送缓冲器 。

公开(公告)号：US08230142B1

公开(公告)日：2012-07-24

申请号：US12122212

申请日：2008-05-16

申请人： Carl F. Rohrer ,  Stacey Secatch

发明人： Carl F. Rohrer ,  Stacey Secatch

IPC分类号： G06F3/00

CPC分类号： G06F15/167

摘要： In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.

摘要翻译： 在一个实施例中，公开了一种设备。 例如，在本发明的一个实施例中，该设备包括具有共享缓冲器的存储器核心和用于从多个处理源的处理源接收目的地就绪信号的仲裁逻辑模块。 该设备还包括至少一个流水线级，用于存储从共享缓冲器读取的至少一条数据，以及至少一个匹配流水线级，其存储与从共享缓冲器读取的至少一条数据相关联的至少一个有效信号 。 该设备还包括用于存储值的计数器，其中该值表示从共享缓冲器读取但尚未传送到处理源的数量的数据。