公开(公告)号：US20090003370A1

公开(公告)日：2009-01-01

申请号：US11847839

申请日：2007-08-30

申请人： Sushil Kering ,  Neeraj Kashalkar ,  Stephen A. Mueller

发明人： Sushil Kering ,  Neeraj Kashalkar ,  Stephen A. Mueller

IPC分类号： H04L12/56

CPC分类号： H04L1/0045

摘要： A system and method for improved performance by a DVB-H receiver is described that allows good Internet Protocol (IP) packets in a Multiprotocol Encapsulation-Forward Error Correction (MPE-FEC) frame to be salvaged even when there are other IP packets in the frame that may have bytes in error after the performance of MPE-FEC operations. To achieve this, the system and method provides a means for ascertaining where IP packets loaded into a memory begin and end in a manner that can be relied upon even when individual bytes of the IP packets, such as certain bytes of the IP packet header used to determine total packet length, may be in error.

摘要翻译： 描述了一种通过DVB-H接收机改进性能的系统和方法，其允许在多协议封装前向纠错（MPE-FEC）帧中的良好互联网协议（IP）分组被抢救，即使当在其中存在其他IP分组时 在执行MPE-FEC操作后可能会出现错误字节的帧。 为了实现这一点，系统和方法提供了一种用于确定加载到存储器中的IP分组何时开始和结束的方式，即使在IP分组的各个字节（例如，使用的IP分组报头的某些字节） 确定总包长度，可能是错误的。

公开(公告)号：US20080317185A1

公开(公告)日：2008-12-25

申请号：US11874748

申请日：2007-10-18

申请人： Stephen A. Mueller ,  Jeffrey Putnam ,  Xuguang (Gary) Zhang

发明人： Stephen A. Mueller ,  Jeffrey Putnam ,  Xuguang (Gary) Zhang

IPC分类号： H03D3/24

CPC分类号： H03D3/006 ,  H03L7/07 ,  H04W52/0229 ,  Y02D70/142 ,  Y02D70/168

摘要： The clock generating portion of a communication system includes a low-power, high-jitter phase locked loop (PLL) and a high-power, low-jitter PLL. Control logic within the chip allows for selective switching between the low-power and high-power PLL for receiving the broadcast signals, such as mobile TV signals. The switching may occur in a manner that is dependent on the conditions of the wireless channel and/or the complexity of the modulation scheme being used. The switching may be used to provide an oscillating signal from one or both of the PLLs to a receiver to be used to receive communication signals. The control logic may power off one of the PLLs to save power when not in use.

摘要翻译： 通信系统的时钟产生部分包括低功率，高抖动锁相环（PLL）和大功率低抖动PLL。 芯片内的控制逻辑允许在用于接收诸如移动电视信号的广播信号的低功率和高功率PLL之间的选择性切换。 切换可以以取决于无线信道的条件和/或正在使用的调制方案的复杂性的方式发生。 切换可用于提供从一个或两个PLL到待接收通信信号的接收机的振荡信号。 控制逻辑可以关闭其中一个PLL，以在不使用时节省电量。

公开(公告)号：US20090027561A1

公开(公告)日：2009-01-29

申请号：US11782166

申请日：2007-07-24

申请人： Christopher Cytera ,  Stephen A. Mueller ,  Xuguang (Gary) Zhang

发明人： Christopher Cytera ,  Stephen A. Mueller ,  Xuguang (Gary) Zhang

IPC分类号： H04N5/46

CPC分类号： H04N5/46 ,  H04N5/4401 ,  H04N5/63 ,  H04N21/41407 ,  H04N21/4183 ,  H04N21/426 ,  H04N21/43632 ,  H04N21/4382 ,  H04N21/4436 ,  H04N21/6131

摘要： Methods, systems, and apparatuses for enabling mobile TV functionality and universal serial bus (USB) functionality are provided. In an example aspect, a mobile television (TV) system includes a mobile TV receiver module and a universal serial bus (USB) interface. The mobile TV receiver module receives a radio frequency (RF) mobile TV signal that includes TV data, and generates a mobile TV data signal that includes the TV data. The USB interface receives the mobile TV data signal, and generates a USB output data signal that includes the TV data. In an aspect, the mobile TV functionality and USB functionality are provided in an integrated circuit chip. In one example, the mobile TV functionality and USB functionality share at least one power supply. In another example, the mobile TV functionality and USB functionality are powered by respective power supplies that are electrically isolated from each other. In such a chip configuration, the chip may be incorporated in a first device that utilizes the USB functionality of the chip, or in a second device that withholds power from the USB functionality.

摘要翻译： 提供了用于实现移动电视功能和通用串行总线（USB）功能的方法，系统和装置。 在示例方面，移动电视（TV）系统包括移动TV接收机模块和通用串行总线（USB）接口。 移动电视接收机模块接收包括TV数据的射频（RF）移动电视信号，并生成包括TV数据的移动TV数据信号。 USB接口接收移动电视数据信号，并产生包括TV数据的USB输出数据信号。 在一方面，移动电视功能和USB功能被提供在集成电路芯片中。 在一个示例中，移动电视功能和USB功能共享至少一个电源。 在另一示例中，移动电视功能和USB功能由彼此电隔离的相应电源供电。 在这样的芯片配置中，芯片可以被并入利用芯片的USB功能的第一设备中，或者在保持来自USB功能的功率的第二设备中。

公开(公告)号：US20080320544A1

公开(公告)日：2008-12-25

申请号：US12124931

申请日：2008-05-21

申请人： Neeraj Kashalkar ,  Christopher den Haan ,  Hongfan Wang ,  Sushil Kering ,  Stephen A. Mueller

发明人： Neeraj Kashalkar ,  Christopher den Haan ,  Hongfan Wang ,  Sushil Kering ,  Stephen A. Mueller

IPC分类号： H04N7/173

CPC分类号： H04N21/8166 ,  H04H40/18 ,  H04N21/4436 ,  H04N21/64315 ,  Y02D70/168

摘要： A hardware-implemented video broadcasting receiver is described. The hardware-implemented video broadcasting receiver includes a radio frequency (RF) tuner, a demodulator connected to the RF tuner, link layer logic connected to the demodulator, and a power manager connected to the RF tuner, the demodulator and the link layer logic. The power manager is configured to receive delta-T values extracted from a transport stream by the link layer logic, to determine whether each of the RF tuner, the demodulator and the link layer logic can be powered down based on the delta-T values, and to power down the RF tuner, the demodulator and the link layer logic based on the determination, thereby reducing the average power consumed by the video broadcasting receiver.

摘要翻译： 描述硬件实现的视频广播接收机。 硬件实现的视频广播接收机包括射频（RF）调谐器，连接到RF调谐器的解调器，连接到解调器的链路层逻辑以及连接到RF调谐器，解调器和链路层逻辑的电源管理器。 功率管理器被配置为从链路层逻辑接收从传输流提取的Δ-T值，以确定RF调谐器，解调器和链路层逻辑中的每一个是否可以基于Δ-T值被掉电， 并且基于该确定来关闭RF调谐器，解调器和链路层逻辑，从而降低视频广播接收机消耗的平均功率。