公开(公告)号：US07490308B2

公开(公告)日：2009-02-10

申请号：US11278162

申请日：2006-03-31

Applicant: Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

Inventor： Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/08

Abstract: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

Abstract translation: 修改用于性能优化的VLSI布局的方法包括为要修改的多个原始设备形状定义修改的基本规则集，并将多个原始设备形状平坦化为主单元。 基于经修改的基础规则集，对平坦化的设备形状执行布局优化操作，以便创建多个修改的设备形状。 然后从修改的设备形状和原始设备形状之间的差异创建覆盖单元。