公开(公告)号：US20190171575A1

公开(公告)日：2019-06-06

申请号：US16264447

申请日：2019-01-31

申请人： Wei CHEN ,  Eswaramoorthi NALLUSAMY ,  Larisa NOVAKOVSKY ,  Mark SCHMISSEUR ,  Eric RASMUSSEN ,  Stephen VAN DOREN ,  Yen-Cheng LIU

发明人： Wei CHEN ,  Eswaramoorthi NALLUSAMY ,  Larisa NOVAKOVSKY ,  Mark SCHMISSEUR ,  Eric RASMUSSEN ,  Stephen VAN DOREN ,  Yen-Cheng LIU

IPC分类号： G06F12/0891 ,  G06F12/02 ,  G06F12/0802

摘要： Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

公开(公告)号：US20190042430A1

公开(公告)日：2019-02-07

申请号：US15670171

申请日：2017-08-07

申请人： RAJESH SANKARAN ,  ISHWAR AGARWAL ,  STEPHEN VAN DOREN

发明人： RAJESH SANKARAN ,  ISHWAR AGARWAL ,  STEPHEN VAN DOREN

IPC分类号： G06F12/0831 ,  G06F12/084

摘要： Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

公开(公告)号：US20060095673A1

公开(公告)日：2006-05-04

申请号：US11258586

申请日：2005-10-25

申请人： Stephen Van Doren ,  Gregory Tierney

发明人： Stephen Van Doren ,  Gregory Tierney

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0808

摘要： The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.

公开(公告)号：US20050198192A1

公开(公告)日：2005-09-08

申请号：US10761047

申请日：2004-01-20

申请人： Stephen Van Doren ,  Gregory Tierney ,  Simon Steely

发明人： Stephen Van Doren ,  Gregory Tierney ,  Simon Steely

IPC分类号： G06F15/16 ,  G06F15/173

CPC分类号： G06F12/0815

摘要： A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.

摘要翻译： 系统包括提供数据广播请求的第一节点。 第一节点从第一节点接收对广播请求的读冲突响应。 读取冲突响应指示第二个节点具有针对数据的未决广播读取请求。 响应于来自第一节点的广播请求，第三节点向第一节点提供所请求的数据。 第一节点填充与第一节点相关联的高速缓存中的第三节点提供的数据。

公开(公告)号：US20050160237A1

公开(公告)日：2005-07-21

申请号：US10760652

申请日：2004-01-20

申请人： Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

发明人： Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0828 ,  G06F2212/2542

摘要： A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.

摘要翻译： 系统包括用于提供源广播请求数据的第一节点。 响应于从存储器接收数据的副本并且从系统中的其他节点接收非数据响应，第一节点将F状态与数据的副本相关联。 非数据响应包括至少第二节点包括数据的共享副本的指示。 F状态使得第一节点能够用作系统中能够利用数据的共享副本响应来自系统中其他节点的请求的系统中的订购点。

公开(公告)号：US20050160209A1

公开(公告)日：2005-07-21

申请号：US10760813

申请日：2004-01-20

申请人： Stephen Van Doren ,  Gregory Tierney ,  Simon Steely

发明人： Stephen Van Doren ,  Gregory Tierney ,  Simon Steely

IPC分类号： G06F12/08 ,  G06F13/38

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0828

摘要： A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.

摘要翻译： 系统包括采用源广播协议来发起事务的第一节点。 如果源广播协议不能提供事务的确定性分辨率，则第一节点采用前进进程协议来解决事务。

公开(公告)号：US20050160132A1

公开(公告)日：2005-07-21

申请号：US10758352

申请日：2004-01-15

申请人： Stephen Van Doren ,  Simon Steely ,  Gregory Tierney

发明人： Stephen Van Doren ,  Simon Steely ,  Gregory Tierney

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0828 ,  G06F12/0831

摘要： One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.

摘要翻译： 一个公开的实施例可以包括系统，其包括家庭节点，其响应于来自请求者的请求向请求者提供事务参考。 请求者响应于事务参考向家庭节点提供确认消息，事务参考使得请求者能够相对于来自请求者的请求确定家庭节点处的请求的顺序。

公开(公告)号：US20060041724A1

公开(公告)日：2006-02-23

申请号：US10920759

申请日：2004-08-17

申请人： Simon Steely ,  Stephen Van Doren

发明人： Simon Steely ,  Stephen Van Doren

IPC分类号： G06F12/00

CPC分类号： G06F12/0815

摘要： A technique to share cache lines among a plurality of bus agents. Embodiments of the invention comprise at least one technique to allow a number of agents, such as a processor or software program being executed by a processor, within a computer system or computer network to access a locked (“owned”) cache line, under certain circumstances, without incurring as much of the operational overhead and resulting performance degradation of many prior art techniques.

摘要翻译： 一种用于在多个总线代理之间共享高速缓存行的技术。 本发明的实施例包括至少一种技术，以允许在计算机系统或计算机网络内的许多代理（诸如处理器或软件程序）由计算机系统或计算机网络中执行以访问锁定（“拥有”）高速缓存行 情况，而不会导致许多现有技术技术的操作开销和所导致的性能下降。

公开(公告)号：US20050160232A1

公开(公告)日：2005-07-21

申请号：US10760651

申请日：2004-01-20

申请人： Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

发明人： Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0831

摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.

摘要翻译： 公开了用于不同高速缓存一致性协议之间的交互的系统和方法。 一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。 第二节点向来自家节点的数据的请求提供冲突响应。 冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。

公开(公告)号：US06353876B1

公开(公告)日：2002-03-05

申请号：US09643431

申请日：2000-08-22

申请人： Paul M. Goodwin ,  Stephen Van Doren

发明人： Paul M. Goodwin ,  Stephen Van Doren

IPC分类号： G06F1208

CPC分类号： G06F12/0813 ,  G06F12/0804 ,  G06F12/0882

摘要： Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping “fill” requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the “victim” data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.

摘要翻译： 改进了多处理器系统中的数据一致性，并且通过使用来自多处理器CPU中的任何一个的数据映射“填充”请求来使数据延迟最小化，使得通过来自相同存储器模块的交叉开关获得所请求的信息，“AD” “CPU缓存中的数据必须重写。 通过这样的布置，在横梁开关内的受害者数据的重写延迟时间被最小化并且避免了“夜间交船”问题。