公开(公告)号：US6038179A

公开(公告)日：2000-03-14

申请号：US224776

申请日：1999-01-04

申请人： Steven Michael Eustis ,  Cheryl Jean Herdey ,  Eric Stephen Machat ,  Dale Edward Pontius ,  Endre Philip Thoma

发明人： Steven Michael Eustis ,  Cheryl Jean Herdey ,  Eric Stephen Machat ,  Dale Edward Pontius ,  Endre Philip Thoma

IPC分类号： G11C5/02 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A Random Access Memory including a redundancy scheme wherein redundant memory elements are organized in a mixture of redundancy patches of various sizes, i.e., various number of word/ bit lines in each patch. The number of lines, e.g., 1, 2, 4 or 8 word or bit lines, in each of the patches is selected as appropriate with many different sized patches existing within the same redundancy reservoir. The size the particular patch selected depends on the size of the replaced defect detected during programming.

摘要翻译： 一种包括冗余方案的随机存取存储器，其中冗余存储器元件被组织成各种尺寸的冗余补丁的混合，即每个补丁中的各种数量的字/位线。 在相同的冗余存储器中存在许多不同大小的补丁，适当地选择每个补丁中的行数，例如1,2,4或8个字或位线。 所选择的特定补丁的大小取决于编程期间检测到的替换缺陷的大小。

公开(公告)号：US07007214B2

公开(公告)日：2006-02-28

申请号：US10604194

申请日：2003-06-30

申请人： Steven Michael Eustis ,  Leah Marie Pfeifer Pastel ,  Thomas Richard Bednar ,  Thomas Gregory Sopchak ,  Jeffery Howard Oppold

发明人： Steven Michael Eustis ,  Leah Marie Pfeifer Pastel ,  Thomas Richard Bednar ,  Thomas Gregory Sopchak ,  Jeffery Howard Oppold

IPC分类号： G01R31/28 ,  G06F7/02

CPC分类号： G01R31/31855

摘要： A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

摘要翻译： 一种用于定位不同扫描链中的连接器缺陷的方法和系统，所述缺陷扫描链在不同布线级上具有并联的无缺陷扫描链，其中两个扫描链以规则阵列图案布置。 预定的位序列被扫描到有缺陷的扫描链中。 然后将有缺陷的扫描链的内容平行移入无缺陷扫描链。 然后将无缺陷扫描链的内容扫描出来并与预定比特序列进行比较。 扫描出的比特与预定比特序列的比较便于在缺陷扫描链中发生连接器缺陷的物理和逻辑地定位。

公开(公告)号：US06675273B2

公开(公告)日：2004-01-06

申请号：US09871057

申请日：2001-05-31

申请人： Steven Michael Eustis ,  Robert Lloyd Barry ,  Peter Francis Croce

发明人： Steven Michael Eustis ,  Robert Lloyd Barry ,  Peter Francis Croce

IPC分类号： G06F1300

CPC分类号： G11C7/227 ,  G11C8/00

摘要： A memory circuitry is designed to efficiently obtain a predictable array output when an invalid address is requested. The memory circuit comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.

摘要翻译： 存储器电路被设计为当请求无效地址时有效地获得可预测的阵列输出。 除了标准有效字线路径之外，存储器电路还包括无效字线路径。 为了提供正确的输出，第一解码逻辑的虚拟字线输出被延迟，并且延迟的虚拟字线输出与字线输出进行“与”运算以更新数据输出锁存器。 此外，第二解码逻辑的无效字线输出也被延迟，并且延迟的无效字线输出与被延迟的虚拟字线输出进行“或”运算以复位控制逻辑。 对延迟的信号进行或运算允许在相同的时钟时间提供可预测的输出，而不管有效地址或无效地址是否被解码。