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公开(公告)号：US08413018B2
公开(公告)日：2013-04-02
申请号：US12542583
申请日：2009-08-17
IPC分类号： H03M13/00
CPC分类号： G06F11/1016 , H03M13/09
摘要： A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated.
摘要翻译： 可编程设备对写入第一存储器的数据采用地址和数据损坏逻辑。 从存储在第一存储器中的数据计算出第一签名并存储在第二存储器中。 当从第一存储器读取数据时，存储在第二存储器中的第一签名被读取并与从从第一存储器读取的数据计算出的第二签名进行比较。 如果第一个和第二个签名不匹配，则会显示错误条件。
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公开(公告)号：US20070211640A1
公开(公告)日：2007-09-13
申请号：US11373711
申请日：2006-03-10
CPC分类号： H04L49/555 , H04L43/50 , H04L49/357
摘要： A method, system or switch device, the switch device having both switch and test capabilities. A method includes running in a test or switch mode or both; and, performing the testing operation or the switching operations, or both. Another method includes setting up the test functionality in the switch device, the test functionality including one or both of transmitting test data and receiving test data. Other steps may include initiating the transmission of test data; and checking the test data. A switch device may include an ASIC disposed within the switch device, the ASIC including one or both of an egress test block and an ingress test block; whereby the egress test block and the ingress test block are respectively adapted to transmit and receive a test packet; whereby the ASIC and one or both of the egress and ingress test blocks provide for alternatively operating in the conventional switch mode and in test mode.
摘要翻译： 一种方法，系统或开关装置，开关装置具有开关和测试能力。 一种方法包括以测试或切换模式运行或两者兼而有之; 并且执行测试操作或切换操作，或两者。 另一种方法包括设置交换设备中的测试功能，测试功能包括发送测试数据和接收测试数据中的一个或两个。 其他步骤可以包括启动测试数据的传输; 并检查测试数据。 开关设备可以包括设置在开关设备内的ASIC，ASIC包括出口测试块和入口测试块中的一个或两个; 由此出口测试块和入口测试块分别适于发送和接收测试分组; 由此ASIC和出口和入口测试块中的一个或两个提供在常规的开关模式和测试模式下的可替代地操作。
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公开(公告)号：US20070147364A1
公开(公告)日：2007-06-28
申请号：US11317995
申请日：2005-12-22
申请人： Subbarao Palacharla , Yu Fang , Joseph Chamdani
发明人： Subbarao Palacharla , Yu Fang , Joseph Chamdani
CPC分类号： H04L45/00 , H04L45/583 , H04L49/45
摘要： A method, system or switch device, the switch device including an ASIC creating a switching system within the switch device, the ASIC including an ingress packet processor, an egress packet assembly device, a transmit control device and a routing device; whereby the ingress packet processor is disposed to receive a data packet, the routing device is adapted to route the data packet from the ingress packet processor to the egress packet assembly device and the transmit control device is disposed to control the routing of the routing device; the switch device further including an ingress port communicating with the ASIC and being connectable to one or more external computer network devices, the ingress port being a substantially standard switch port; an egress port communicating with the ASIC and being connectable to one or more external computer network devices, the egress port being a substantially standard switch port; and, an extender port, the extender port being connectable to another extender port in loopback fashion and being connectable to a corresponding extender port of a discrete switch device, whereby the extender port operates on a discrete protocol from the standard ports; whereby the ASIC is adapted to provide for alternatively transmitting a data packet locally to the egress port and remotely through the extender port.
摘要翻译： 一种方法，系统或交换设备，所述交换设备包括在所述交换设备内创建交换系统的ASIC，所述ASIC包括入口分组处理器，出口分组组装设备，发射控制设备和路由设备; 由此入口分组处理器被设置为接收数据分组，路由设备适于将数据分组从入口分组处理器路由到出口分组组装设备，并且发送控制设备被设置为控制路由设备的路由; 所述交换设备还包括与所述ASIC通信并可连接到一个或多个外部计算机网络设备的入口，所述入口是基本上标准的交换机端口; 与所述ASIC通信并可连接到一个或多个外部计算机网络设备的出口端口，所述出口是基本上标准的交换机端口; 扩展器端口可以环回方式连接到另一扩展器端口，并且可连接到离散交换设备的对应扩展器端口，由此扩展器端口从标准端口以离散协议操作; 由此ASIC适于提供将数据分组本地地发送到出口端口并且通过扩展器端口远程地发送。
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公开(公告)号：US20110041031A1
公开(公告)日：2011-02-17
申请号：US12542583
申请日：2009-08-17
CPC分类号： G06F11/1016 , H03M13/09
摘要： A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated.
摘要翻译： 可编程设备对写入第一存储器的数据采用地址和数据损坏逻辑。 从存储在第一存储器中的数据计算出第一签名并存储在第二存储器中。 当从第一存储器读取数据时，存储在第二存储器中的第一签名被读取并与从从第一存储器读取的数据计算出的第二签名进行比较。 如果第一个和第二个签名不匹配，则会显示错误条件。
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公开(公告)号：US20090097495A1
公开(公告)日：2009-04-16
申请号：US11870922
申请日：2007-10-11
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： Flexible virtual queues of a switch are allocated to provide non-blocking virtual output queue (VOQ) support. A port ASIC has a set of VOQs, one VOQ per supported port of the switch. For each VOQ, a set of virtual input queues (VIQs) includes a VIQ for each input port of the port ASIC that forms a non-blocking flow with the corresponding output port (and potentially, with the specified level of service) in the switch. The port ASIC selects a VOQ for transmission and then arbitrates among the VIQs of the selected VOQ to select a VIQ from which to transmit the packet. Having identified an appropriate VIQ, the port ASIC transmits cells of the packet at the head of the VIQ to a port ASIC that includes the corresponding output port for reassemble and eventual transmission through the output port.
摘要翻译： 分配交换机的灵活虚拟队列以提供非阻塞虚拟输出队列（VOQ）支持。 端口ASIC具有一组VOQ，每个支持的交换机端口一个VOQ。 对于每个VOQ，一组虚拟输入队列（VIQ）包括端口ASIC的每个输入端口的VIQ，其形成具有相应输出端口（并且潜在地具有指定的服务级别）的非阻塞流程 。 端口ASIC选择用于传输的VOQ，然后在所选择的VOQ的VIQ之间进行仲裁以选择从其发送分组的VIQ。 在确定了适当的VIQ之后，端口ASIC将在VIQ的头部的数据包的单元发送到包括相应的输出端口的端口ASIC，以通过输出端口重新组合和最终传输。
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公开(公告)号：US5761706A
公开(公告)日：1998-06-02
申请号：US333133
申请日：1994-11-01
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines whether a pattern of references has a predetermined relationship, and if so, prefetches stream data into the cache block storage area. Such stream data prefetches are particularly useful in vector processing computers, where once the processor starts to fetch a vector, the addresses of future fetches can be predicted based in the pattern of past fetches. According to various aspects of the present invention, the filtered stream buffer further includes a history table, a validity indicator which is associated with the cache block storage area and indicates which cache blocks, if any, are valid. According to yet another aspect of the present invention, the filtered stream buffer controls random access memory (RAM) chips to stream the plurality of consecutive cache blocks from the RAM into the cache block storage area. According to yet another aspect of the present invention, the stream data includes data for a plurality of strided cache blocks, wherein each of which these strided cache blocks corresponds to an address determined by adding to the first address an integer multiple of the difference between the second address and the first address. According to yet another aspect of the present invention, the processor generates three addresses of data words in the memory, and the filter controller determines whether a predetermined relationship exists among three addresses, and if so, prefetches strided stream data into said cache block storage area.
摘要翻译： 耦合到存储器和处理器的经滤波的流缓冲器的方法和装置，并且用于从存储器预取数据。 滤波的流缓冲器包括高速缓存块存储区域和过滤器控制器。 滤波器控制器确定引用模式是否具有预定关系，如果是，则将流数据预取到高速缓存块存储区域中。 这样的流数据预取在向量处理计算机中特别有用，其中一旦处理器开始获取向量，可以基于过去提取的模式来预测未来提取的地址。 根据本发明的各个方面，滤波流缓冲器还包括历史表，与高速缓存块存储区相关联的有效性指示符，并指示哪些高速缓存块（如果有的话）是有效的。 根据本发明的另一方面，滤波流缓冲器控制随机存取存储器（RAM）芯片以将多个连续高速缓存块从RAM流入高速缓存块存储区域。 根据本发明的另一方面，流数据包括用于多个跨度高速缓存块的数据，其中这些跨越高速缓存块中的每一个对应于通过将第一地址相加的确定的地址， 第二个地址和第一个地址。 根据本发明的另一方面，处理器在存储器中产生数据字的三个地址，并且滤波器控制器确定在三个地址之间是否存在预定的关系，如果是，则将步进流数据预取到所述高速缓存块存储区域 。
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